首頁 數據轉換器 類比轉數位轉換器 (ADC) 高速 ADC (≥10 MSPS)
首頁
數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)
最新

ADC3683-SP

現行

抗輻射保證 (RHA)、QMLV、300-krad、18 位元、2 通道 65MSPS 低延遲低功率 ADC

立即訂購
產品規格表

ADC3683-SP

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 65 Resolution (Bits) 18 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 400 Features High Dynamic Range, High Performance, Low Power Rating Space Peak-to-peak input voltage range (V) 3.2 Power consumption (typ) (mW) 186 Architecture SAR SNR (dB) 83 ENOB (bit) 13.5 SFDR (dB) 85 Operating temperature range (°C) 25 to 25 Input buffer No Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 75
Sample rate (max) (Msps) 65 Resolution (Bits) 18 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 400 Features High Dynamic Range, High Performance, Low Power Rating Space Peak-to-peak input voltage range (V) 3.2 Power consumption (typ) (mW) 186 Architecture SAR SNR (dB) 83 ENOB (bit) 13.5 SFDR (dB) 85 Operating temperature range (°C) 25 to 25 Input buffer No Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 75
CFP (HBP) 64 118.81 mm² 10.9 x 10.9
  • Space screening and radiation performance
    • QML-V screening and reliability
    • Total ionizing dose (TID): 300 krad (Si)
    • Single event latchup (SEL): 75 MeV-cm2/mg
  • Ambient temperature range: ­−55°C to 105°C
  • Dual channel ADC
  • 18-bit 65MSPS
  • Noise Floor: -160dBFS/Hz
  • Low power and optimized power scaling: 50mW/ch (10MSPS) to 94mW/ch (65MSPS)
  • Latency: 1-2 clock cycles
  • 18-bit, no missing codes
  • INL: ±9, DNL: ±0.7 LSB (typical)
  • Reference: external or internal
  • Input bandwidth: 140MHz (–3dB)
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • Serial LVDS digital interface (2-, 1- and 1/2-wire)
  • Spectral performance (fIN = 5MHz):
    • SNR: 83.5dBFS
    • SFDR: 87dBc HD2, HD3
    • SFDR: 99dBFS worst spur
  • Space screening and radiation performance
    • QML-V screening and reliability
    • Total ionizing dose (TID): 300 krad (Si)
    • Single event latchup (SEL): 75 MeV-cm2/mg
  • Ambient temperature range: ­−55°C to 105°C
  • Dual channel ADC
  • 18-bit 65MSPS
  • Noise Floor: -160dBFS/Hz
  • Low power and optimized power scaling: 50mW/ch (10MSPS) to 94mW/ch (65MSPS)
  • Latency: 1-2 clock cycles
  • 18-bit, no missing codes
  • INL: ±9, DNL: ±0.7 LSB (typical)
  • Reference: external or internal
  • Input bandwidth: 140MHz (–3dB)
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • Serial LVDS digital interface (2-, 1- and 1/2-wire)
  • Spectral performance (fIN = 5MHz):
    • SNR: 83.5dBFS
    • SFDR: 87dBc HD2, HD3
    • SFDR: 99dBFS worst spur

The ADC3683-SP is a low noise, ultra-low power 18-bit 65MSPS high-speed dual channel ADC. Designed for lowest noise performance, the device delivers a noise spectral density of −160dBFS/Hz combined with excellent linearity and dynamic range. The ADC3683-SP offers DC precision together with IF sampling support making it designed for a wide range of applications. High-speed control loops benefit from the short latency as low as only 1 clock cycle. The ADC consumes only 94mW/ch at 65Msps and the power consumption scales well with lower sampling rates.

The device uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device supports two-lane, one-lane and half-lane options. The device is pin-to-pin compatible with the 14-bit, 125MSPS ADC3664-SP. The device comes in a 64-pin CFP package (10.9mm x 10.9mm), and supports a temperature range from −55°C to +105°C.

The ADC3683-SP is a low noise, ultra-low power 18-bit 65MSPS high-speed dual channel ADC. Designed for lowest noise performance, the device delivers a noise spectral density of −160dBFS/Hz combined with excellent linearity and dynamic range. The ADC3683-SP offers DC precision together with IF sampling support making it designed for a wide range of applications. High-speed control loops benefit from the short latency as low as only 1 clock cycle. The ADC consumes only 94mW/ch at 65Msps and the power consumption scales well with lower sampling rates.

The device uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device supports two-lane, one-lane and half-lane options. The device is pin-to-pin compatible with the 14-bit, 125MSPS ADC3664-SP. The device comes in a 64-pin CFP package (10.9mm x 10.9mm), and supports a temperature range from −55°C to +105°C.
open-in-new 尋找其它 高速 ADC (≥10 MSPS)
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 2
類型 標題 日期
* Data sheet ADC3683-SP Space Grade 18-Bit 1 to 65MSPS, Low Noise, Ultra-low Power Dual Channel ADC datasheet PDF | HTML 2024年 3月 8日
EVM User's guide ADC36xxEVMCVAL Evaluation Module User's Guide PDF | HTML 2023年 12月 4日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

ADC3683EVMCVAL — ADC3683-SP 評估模組

<p>ADC3683EVMCVAL 用於評估 ADC3683-SP 類比轉數位轉換器 (ADC)。ADC3683-SP 使用序列低電壓差動訊號 (LVDS) 介面來輸出數位資料。序列化 LVDS 介面支援高達 1Gbps 的輸出速率。ADC3683-SP 可透過內部抽取濾波器在超取樣 + 抽取模式下運作，可提高動態範圍並放鬆外部抗混疊濾波器。<‌/p>

使用指南: PDF | HTML
TI.com 無法提供
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
要求
封裝 引腳 下載
CFP (HBP) 64 檢視選項
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 資格摘要
  • 進行中可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片