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邏輯和電壓轉換
正反器、鎖存器和暫存器
D 型正反器

CD40174B-MIL

現行

CMOS 六路 D 型正反器

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產品規格表

CD40174B-MIL

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 6 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 8 IOL (max) (mA) 6.8 IOH (max) (mA) -6.8 Supply current (max) (µA) 600 Features Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 6 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 8 IOL (max) (mA) 6.8 IOH (max) (mA) -6.8 Supply current (max) (µA) 600 Features Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • 5-V, 10-V, and 15-V parametric ratings
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
            1 V at VDD = 5 V
            2 V at VDD = 10 V
         2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • Shift Registers
    • Buffer/Storage Registers
    • Pattern Generators
  • 5-V, 10-V, and 15-V parametric ratings
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
            1 V at VDD = 5 V
            2 V at VDD = 10 V
         2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • Shift Registers
    • Buffer/Storage Registers
    • Pattern Generators

Cd40174B consists of six identical ’D’-type flip-flops having independent DATA inputs. The CLOCK and CLEAR\ inputs are common to all six units. Data are transferred to the Q outputs on the positive-going transition of the clock pulse. All sic flip-flops are simultaneously reset by a low level on the CLEAR\ input.

The CD40174B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

Cd40174B consists of six identical ’D’-type flip-flops having independent DATA inputs. The CLOCK and CLEAR\ inputs are common to all six units. Data are transferred to the Q outputs on the positive-going transition of the clock pulse. All sic flip-flops are simultaneously reset by a low level on the CLEAR\ input.

The CD40174B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
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類型 標題 日期
* Data sheet CD40174B TYPES datasheet (Rev. C) 2003年 10月 13日
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 2001年 12月 3日

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