CD4097B
- Low ON resistance: 125
(typ.) over 15 Vp-p signal-input range for VDD - VSS = 15 V - High OFF resistance: channel leakage of ±10 pA (typ.) @ VDD - VSS = 10 V
- Matched switch characteristics: RON = 5 (typ.) for VDD - VSS = 15 V
- Very low quiescent power dissipation under all digital-control input and supply conditions: 0.2 uW (typ.) @ VDD - VSS = 10 V
- Binary address decoding on chip
- 5-V, 10-V, and 15-V parametric ratings
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100nA at 18 V and 25°C
- Meets all requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications:
- Analog and digital multiplexing and demultiplexing
- A/D and D/A conversion
- Siganl gating
* When these devices are used as demultiplexers, the channel in/out terminals are the outputs and the common out/in terminals are the inputs.
CD4067B and CD4097B CMOS analog multiplexers/demultiplexers* are digitally controlled analog switches having low ON impedance, low OFF leakage current, and internal address decoding. In addition, the ON resistance is relatively constant over the full input-signal range. The CD4067B is a 16-channel multiplexer with four binary control inputs, A, B, C, D, and an inhibit input, arranged so that any combination of the inputs selects one switch.
The CD4097B is a differential 8-channel multiplexer having three binary control inputs, A, B, C, and an inhibit input. The inputs permit selection of one of eight pairs of switches.
A logic "1" present at the inhibit input turns all channels off.
The CD4067B and CD4097B types are supplied in 24-lead hermetic dual-in-line ceramic packages (F3A suffix), 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR suffixes), and 24-lead thin shrink small-outline packages (P and PWR suffixes).
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CD4067B, CD4097B TYPES datasheet (Rev. B) | 2003年 6月 16日 | |
| Application note | Selecting the Correct Texas Instruments Signal Switch (Rev. E) | PDF | HTML | 2022年 6月 2日 | |
| Application note | Multiplexers and Signal Switches Glossary (Rev. B) | PDF | HTML | 2021年 12月 1日 | |
| Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
| User guide | Signal Switch Data Book (Rev. A) | 2003年 11月 14日 | ||
| Application note | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | 2001年 12月 3日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
LEADED-ADAPTER1 — 適用於快速測試 TI 的 5、8、10、16 及 24 針腳引線封裝的表面貼裝至 DIP 接頭適配器
The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages. The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.
| 封裝 | 引腳 | 下載 |
|---|---|---|
| SOIC (DW) | 24 | 檢視選項 |
| TSSOP (PW) | 24 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。