CY74FCT543T
- Function, Pinout, and Drive Compatible With FCT and F Logic
- Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
- Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
- Ioff Supports Partial-Power-Down Mode Operation
- Matched Rise and Fall Times
- Fully Compatible With TTL Input and Output Logic Levels
- 3-State Outputs
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- Separation Controls for Data Flow in Each Direction
- Back-to-Back Latches for Storage
- CY54FCT543T
- 48-mA Output Sink Current
- 12-mA Output Source Current
- CY74FCT543T
- 64-mA Output Sink Current
- 32-mA Output Source Current
The \x92FCT543T octal latched transceivers contain two sets of eight D-type latches with separate latch-enable (LEAB\, LEBA\) and output-enable (OEAB\, OEBA\) inputs for each set to permit independent control of input and output in either direction of data flow. For data flow from A to B, for example, the A-to-B enable (CEAB\) input must be low in order to enter data from A or to take data from B, as indicated in the function table. With CEAB\ low, a low signal on the A-to-B latch-enable (LEAB\) input makes the A-to-B latches transparent; a subsequent low-to-high transition of the LEAB\ signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB\ and OEAB\ low, the 3-state B-output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses CEBA\, LEBA\, and OEBA\ inputs.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | 8-Bit Latched Registered Transceivers With 3-State Outputs datasheet (Rev. A) | 2001年 10月 1日 | |
| Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
| Application note | Selecting the Right Level Translation Solution (Rev. A) | 2004年 6月 22日 | ||
| User guide | CYFCT Parameter Measurement Information | 2001年 4月 2日 | ||
| Selection guide | Advanced Bus Interface Logic Selection Guide | 2001年 1月 9日 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 引腳 | 下載 |
|---|---|---|
| SOIC (DW) | 24 | 檢視選項 |
| SSOP (DBQ) | 24 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點