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LVDS、M-LVDS 和 PECL IC

DS90C032QML-SP

現行

LVDS 四 CMOS 差動線路接收器

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產品規格表

DS90C032QML-SP

現行
產品規格表 立即訂購

產品詳細資料

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 5 Signaling rate (MBits) 155.5 Input signal LVDS Output signal TTL Rating Space Operating temperature range (°C) -55 to 125
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 5 Signaling rate (MBits) 155.5 Input signal LVDS Output signal TTL Rating Space Operating temperature range (°C) -55 to 125
CFP (NAC) 16 62.9285 mm² 9.91 x 6.35 CFP (NAD) 16 62.9285 mm² 9.91 x 6.35 DIESALE (Y) — See data sheet
  • Single Event Latchup (SEL) Immune 120 MeV-cm2/mg
  • High Impedance LVDS Inputs with Power-Off.
  • Accepts Small Swing (330 mV) Differential Signal Levels
  • Low Power Dissipation
  • Low Differential Skew
  • Low Chip to Chip Skew
  • Pin Compatible with DS26C32A
  • Compatible with IEEE 1596.3 SCI LVDS Standard

All trademarks are the property of their respective owners.

  • Single Event Latchup (SEL) Immune 120 MeV-cm2/mg
  • High Impedance LVDS Inputs with Power-Off.
  • Accepts Small Swing (330 mV) Differential Signal Levels
  • Low Power Dissipation
  • Low Differential Skew
  • Low Chip to Chip Skew
  • Pin Compatible with DS26C32A
  • Compatible with IEEE 1596.3 SCI LVDS Standard

All trademarks are the property of their respective owners.

The DS90C032 is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.

The DS90C032 accepts low voltage differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions.

The DS90C032 provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.

The DS90C032 and companion line driver (DS90C031) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications.

The DS90C032 is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.

The DS90C032 accepts low voltage differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions.

The DS90C032 provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.

The DS90C032 and companion line driver (DS90C031) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications.
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類型 標題 日期
* Data sheet DS90C032QML LVDS Quad CMOS Differential Line Receiver datasheet (Rev. D) 2013年 4月 12日
* SMD DS90C032QML-SP SMD 5962-95834 2016年 6月 21日
* Radiation & reliability report DS90C032xLQMLV SEE Report 2012年 5月 9日
* Radiation & reliability report DS90C032xLQMLV TID Report 2012年 5月 9日
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 2023年 8月 31日
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 2022年 11月 17日
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022年 10月 19日
Selection guide TI Space Products (Rev. I) 2022年 3月 3日
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 2018年 8月 3日
Application brief How to Terminate LVDS Connections with DC and AC Coupling 2018年 5月 16日
More literature Die D/S DS90C032 MDR Lvds Quad Cmos Differential Line Receiver 2012年 9月 7日
Application note AN-1110 LVDS Quad Dynamic I CC vs Frequency 2004年 5月 15日

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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CFP (NAC) 16 檢視選項
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