DS91D176
- DC to 100+ MHz / 200+ Mbps Low Power, Low EMI Operation
- Optimal for ATCA, uTCA Clock Distribution Networks
- Meets or Exceeds TIA/EIA-899 M-LVDS Standard
- Wide Input Common Mode Voltage for Increased Noise Immunity
- DS91D176 has Type 1 Receiver Input
- DS91C176 has Type 2 Receiver with Fail-safe
- Industrial Temperature Range
- Space Saving SOIC-8 Package
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The DS91C176 and DS91D176 are 100 MHz single channel M-LVDS (Multipoint Low Voltage Differential Signaling) transceivers designed for applications that utilize multipoint networks (e.g. clock distribution in ATCA and uTCA based systems). M-LVDS is a new bus interface standard (TIA/EIA-899) optimized for multidrop networks. Controlled edge rates, tight input receiver thresholds and increased drive strength are sone of the key enhancements that make M-LVDS devices an ideal choice for distributing signals via multipoint networks.
The DS91C176/DS91D176 are half-duplex transceivers that accept LVTTL/LVCMOS signals at the driver inputs and convert them to differential M-LVDS signals. The receiver inputs accept low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL and CML) and convert them to 3V LVCMOS signals. The DS91D176 has a M-LVDS type 1 receiver input with no offset. The DS91C176 has an M-LVDS type 2 receiver which enable failsafe functionality.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS91D176/DS91C176 100 MHz Single Channel M-LVDS Transceivers datasheet (Rev. L) | 2013年 4月 16日 | |
| Application brief | How Far, How Fast Can You Operate MLVDS? | 2018年 8月 6日 | ||
| Application note | Designing an ATCA Compliant M-LVDS Clock Distribution Network (Rev. B) | 2013年 4月 26日 | ||
| Application note | Introduction to M-LVDS (TIA/EIA-899) (Rev. A) | 2013年 1月 3日 | ||
| EVM User's guide | 100 MHz M-LVDS Transceiver Evaluation Board | 2012年 1月 26日 |
設計與開發
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| 封裝 | 引腳 | 下載 |
|---|---|---|
| SOIC (D) | 8 | 檢視選項 |
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