DS92LV3242
- Wide Operating Range Embedded Clock SER/DES
- Up to 32-bit Parallel LVCMOS Data
- 20 to 85 MHz Parallel Clock
- Up to 2.72 Gbps Application Data Paylod
- Selectable Serial LVDS Bus Width
- Dual Lane Mode (20 to 50 MHz)
- Quad Lane Mode (40 to 85 MHz)
- Simplified Clocking Architecture
- No Separate Serial Clock Line
- No reference Clock Required
- Receiver Locks to Random Data
- On-Chip Signal Conditioning for Robust Serial Connectivity
- Transmit Pre-Emphasis
- Data Randomization
- DC-Balance Encoding
- Receive Channel Deskew
- Supports up to 10m CAT-5 at 2.7 Gbps
- Integrated LVDS Terminations
- Built-in AT-SPEED BIST for End-to-End System Testing
- AC-Coupled Interconnect for Isolation and Fault Protection
- > 4KV HBM ESD Protection
- Space-Saving 64-pin TQFP Package
- Full Industrial Temperature Range : -40° to +85°C
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The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or 4 (selectable) embedded clock LVDS serial channels for a data payload rate up to 2.72 Gbps over cables such as CATx, or backplanes FR-4 traces. The companion DS92LV3242 (DES) deserializes the 2 or 4 LVDS serial data channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus.
On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer Pre-emphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing an easy “plug-and-lock” operation.
By embedding the clock in the data payload and including signal conditioning functions, the Channel-Link II SerDes devices reduce trace count, eliminate skew issues, simplify design effort and lower cable/connector cost for a wide variety of video, control and imaging applications. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS92LV3241/3242 20-85 MHz 32-Bit Channel Link II Serializer / Deserializer datasheet (Rev. D) | 2013年 4月 16日 | |
| Application note | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018年 11月 9日 | ||
| Application note | DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) | 2013年 4月 29日 | ||
| Application note | Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des (Rev. A) | 2013年 4月 26日 | ||
| User guide | DS92LV3241/DS92LV3242 Demonstration Kit User Manual | 2012年 1月 25日 | ||
| Design guide | Channel Link II Design Guide | 2011年 1月 21日 |
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