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FPC401

現行

四埠控制器

產品詳細資料

Features I2C aggregation GPIO management Frequency (max) (MHz) 10 Supply restrictions Host side 1.8V to 3.3V Rating Catalog Operating temperature range (°C) -40 to 85
Features I2C aggregation GPIO management Frequency (max) (MHz) 10 Supply restrictions Host side 1.8V to 3.3V Rating Catalog Operating temperature range (°C) -40 to 85
WQFN (RHU) 56 55 mm² 11 x 5
  • Supports Control Signal Management and I2C Aggregation Across Four Ports
  • Combine Multiple FPC401s to Control 56 Total Ports Through a Single Host Interface
  • Eliminates Need for Discrete I2C Muxes, LED Drivers, and High-Pin-Count FPGA/CPLD Control Devices
  • Reduces PCB Routing Complexity by Handling All Low-Speed Control Signals Close to the Port
  • Selectable I2C (Up to 1 MHz) or SPI (Up to 10 MHz) Host Control Interface
  • Automatic Pre-Fetching of Critical, User-Specified Data From the Modules
  • Low Single-Port and Multi-Port Read/Write Latency: <50 µs for SPI Mode, <400 µs for I2C Mode
  • Broadcast Mode Allows Writes to All Ports Simultaneously Across All FPC401 Controllers
  • Advanced LED Features for Port Status Indication, Including Programmable Blinking and Dimming
  • Customizable Interrupt Events
  • Separate Host-Side I/O Voltage: 1.8-V to 3.3-V
  • Small QFN Package Enabling Placement on Bottom Side of PCB Underneath Ports
  • Supports Control Signal Management and I2C Aggregation Across Four Ports
  • Combine Multiple FPC401s to Control 56 Total Ports Through a Single Host Interface
  • Eliminates Need for Discrete I2C Muxes, LED Drivers, and High-Pin-Count FPGA/CPLD Control Devices
  • Reduces PCB Routing Complexity by Handling All Low-Speed Control Signals Close to the Port
  • Selectable I2C (Up to 1 MHz) or SPI (Up to 10 MHz) Host Control Interface
  • Automatic Pre-Fetching of Critical, User-Specified Data From the Modules
  • Low Single-Port and Multi-Port Read/Write Latency: <50 µs for SPI Mode, <400 µs for I2C Mode
  • Broadcast Mode Allows Writes to All Ports Simultaneously Across All FPC401 Controllers
  • Advanced LED Features for Port Status Indication, Including Programmable Blinking and Dimming
  • Customizable Interrupt Events
  • Separate Host-Side I/O Voltage: 1.8-V to 3.3-V
  • Small QFN Package Enabling Placement on Bottom Side of PCB Underneath Ports

The FPC401 quad port controller serves as a low-speed signal aggregator for common port types such as SFP+, QSFP+, and SAS. The FPC401 aggregates all low-speed control and I2C signals across four ports and presents a single easy-to-use management interface to the host (I2C or SPI). Multiple FPC401s can be used in high-port-count applications with one common control interface to the host. The FPC401 is designed to allow placement on the bottom side of the PCB, underneath the press fit connector, to simplify routing. This localized control of the ports’ low-speed signals cuts system BOM cost by enabling the use of smaller IO count control devices (FPGAs, CPLDs, MCUs) and by reducing routing layer congestion.

The FPC401 quad port controller serves as a low-speed signal aggregator for common port types such as SFP+, QSFP+, and SAS. The FPC401 aggregates all low-speed control and I2C signals across four ports and presents a single easy-to-use management interface to the host (I2C or SPI). Multiple FPC401s can be used in high-port-count applications with one common control interface to the host. The FPC401 is designed to allow placement on the bottom side of the PCB, underneath the press fit connector, to simplify routing. This localized control of the ports’ low-speed signals cuts system BOM cost by enabling the use of smaller IO count control devices (FPGAs, CPLDs, MCUs) and by reducing routing layer congestion.

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類型 標題 日期
* Data sheet FPC401 Quad Port Controller datasheet PDF | HTML 2016年 12月 7日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in CMOS Output Buffers PDF | HTML 2024年 5月 14日
EVM User's guide FPC401 and FPC402 Evaluation Module (EVM) User ’s Guide (Rev. B) 2019年 9月 3日
Technical article Solve the challenge of too many wires in high-speed networking equipment PDF | HTML 2017年 1月 26日
More literature Advanced Signal Conditioning Made Easy and Efficient 2017年 1月 12日

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FPC401 IBIS Model

SNLM209.ZIP (222 KB) - IBIS Model
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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