LMH0071
- 5-Bit LVDS Interface
- No External VCO or Clock Required
- Reclocked Serial Loopthrough With Cable Driver
- Powerdown Mode
- 3.3V SMBus Configuration Interface
- Small 48-Pin WQFN Package
- Industrial Temperature range: -40°C to +85°C
Key Specifications
- Output compliant with SMPTE 259M-C, SMPTE 292M, SMPTE 424M and DVB-ASI
- Typical power dissipation: 590 mW (loopthrough disabled, 3G datarate)
- 0.6 UI Minimum Input Jitter Tolerance
All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments.
The LMH0341/0041/0071/0051 SDI Deserializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. When paired with a host FPGA the LMH0341 automatically detects the incoming data rate and decodes the raw 5-bit data words compliant to any of the following standards: DVB-ASI, SMPTE 259M, SMPTE 292M, or SMPTE 424M. See for details on which Standards are supported per device.
The interface between the LMH0341 and the host FPGA consists of a 5-bit wide LVDS bus, an LVDS clock and an SMBus interface. No external VCOs or clocks are required. The LMH0341 CDR detects the frequency from the incoming data stream, generates a clean clock and transmits both clock and data to the host FPGA. The LMH0341, LMH0041 and LMH0071 include a serial reclocked loopthrough with integrated SMPTE compliant cable driver. Refer to for a complete listing of single channel deserializers offered in this family.
The FPGA-Attach SER/DES product family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The product is packaged in a physically small 48 pin WQFN package.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | LMH0341/041/071/051 3Gbps, HD, SD, DVB-ASI SDI Deserializr w/Loopthru & LVDS I/F datasheet (Rev. Q) | 2013年 4月 16日 | |
| Selection guide | Broadcast and Professional Video Interface Solutions (Rev. E) | 2017年 4月 5日 | ||
| Application note | AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) | 2013年 4月 26日 | ||
| Application note | AN-1988 LMH0340 / LMH0341 SerDes Family LVDS Timing Overview (Rev. A) | 2013年 4月 26日 | ||
| Application note | AN-2145 Power Considerations for SDI Products (Rev. B) | 2013年 4月 26日 | ||
| Application note | AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) | 2013年 4月 26日 | ||
| Application note | High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems | 2009年 11月 12日 | ||
| Application note | A 3 Gbps SDI Connectivity Solution Supporting Uncompressed 1080p60 Video | 2008年 3月 18日 | ||
| Design guide | Broadcast Video Owner's Manual | 2006年 11月 17日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
BROADCAST_VIDEO_SERDES_IP — 適用於 LVDS 介面 SDI SerDes 的廣播視訊支援代碼
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 引腳 | 下載 |
|---|---|---|
| WQFN (RHS) | 48 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點