SN54AS885
- Latchable P-Input Ports With Power-Up Clear
- Choice of Logical or Arithmetic
(Two's Complement) Comparison - Data and PLE Inputs Utilize pnp Input Transistors to Reduce dc Loading Effects
- Approximately 35% Improvement in
ac Performance Over Schottky TTL While Performing More Functions - Cascadable to n Bits While Maintaining High Performance
- 10% Less Power Than STTL for an 8-Bit Comparison
- Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
These advanced Schottky devices are capable of performing high-speed arithmetic or logic comparisons on two 8-bit binary or two's complement words. Two fully decoded decisions about words P and Q are externally available at two outputs. These devices are fully expandable to any number of bits without external gates. To compare words of longer lengths, the P > QOUT and P < QOUT outputs of a stage handling less significant bits can be connected to the P > QIN and P < QIN inputs of the next stage handling more significant bits. The cascading paths are implemented with only a two-gate-level delay to reduce overall comparison times for long words. Two alternative methods of cascading are shown in application information.
The latch is transparent when P latch-enable (PLE) input is high;
the P-input port is latched
when PLE is low. This provides the designer with temporary storage for the P-data word. The enable circuitry is implemented with minimal delay times to enhance performance when cascaded for longer words. The PLE, P, and Q data inputs utilize pnp input transistors to reduce the low-level current input requirement to typically -0.25 mA, which minimizes dc loading effects.
The SN54AS885 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS885 is characterized for operation from 0°C to 70°C.
In these cases, P > QOUT follows P > QIN and P < QOUT follows P < QIN.
AG = arithmetically greater than
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | 8-Bit Magnitude Comparators datasheet (Rev. A) | 1995年 1月 1日 | |
| * | SMD | SN54AS885 SMD 5962-89757 | 2016年 6月 21日 | |
| Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002年 8月 29日 | ||
| Application note | Designing With Logic (Rev. C) | 1997年 6月 1日 | ||
| Application note | Advanced Schottky Load Management | 1997年 2月 1日 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996年 10月 1日 | ||
| Application note | Live Insertion | 1996年 10月 1日 | ||
| Application note | Advanced Schottky (ALS and AS) Logic Families | 1995年 8月 1日 |
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訂購與品質
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- 鉛塗層/球物料
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- 材料內容
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