產品詳細資料

Function Counter Bits (#) 4 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Function Counter Bits (#) 4 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 13 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Single Down/Up Count-Control Line
  • Look-Ahead Circuitry Enhances Speed of Cascaded Counters
  • Fully Synchronous in Count Modes
  • Asynchronously Presettable With Load Control

  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 13 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Single Down/Up Count-Control Line
  • Look-Ahead Circuitry Enhances Speed of Cascaded Counters
  • Fully Synchronous in Count Modes
  • Asynchronously Presettable With Load Control

The ’HC191 devices are 4-bit synchronous, reversible, up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.

The outputs of the four flip-flops are triggered on a low- to high-level transition of the clock (CLK) input if the count-enable (CTEN)\ input is low. A high at CTEN\ inhibits counting. The direction of the count is determined by the level of the down/up (D/U\) input. When D/U\ is low, the counter counts up, and when D/U\ is high, it counts down.

These counters feature a fully independent clock circuit. Change at the control (CTEN\ and D/U\) inputs that modifies the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter is dictated solely by the condition meeting the stable setup and hold times.

These counters are fully programmable; that is, each of the outputs can be preset to either level by placing a low on the load (LOAD)\ input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the level of CLK. This feature allows the counters to be used as modulo-N dividers simply by modifying the count length with the preset inputs.

Two outputs are available to perform the cascading function: ripple clock (RCO)\ and maximum/minimum (MAX/MIN) count. MAX/MIN produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down, or maximum (9 or 15) counting up. RCO\ produces a low-level output pulse under those same conditions, but only while CLK is low. The counters can be cascaded easily by feeding RCO\ to CTEN\ of the succeeding counter if parallel clocking is used, or to CLK if parallel enabling is used. MAX/MIN can be used to accomplish look ahead for high-speed operation.

The ’HC191 devices are 4-bit synchronous, reversible, up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.

The outputs of the four flip-flops are triggered on a low- to high-level transition of the clock (CLK) input if the count-enable (CTEN)\ input is low. A high at CTEN\ inhibits counting. The direction of the count is determined by the level of the down/up (D/U\) input. When D/U\ is low, the counter counts up, and when D/U\ is high, it counts down.

These counters feature a fully independent clock circuit. Change at the control (CTEN\ and D/U\) inputs that modifies the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter is dictated solely by the condition meeting the stable setup and hold times.

These counters are fully programmable; that is, each of the outputs can be preset to either level by placing a low on the load (LOAD)\ input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the level of CLK. This feature allows the counters to be used as modulo-N dividers simply by modifying the count length with the preset inputs.

Two outputs are available to perform the cascading function: ripple clock (RCO)\ and maximum/minimum (MAX/MIN) count. MAX/MIN produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down, or maximum (9 or 15) counting up. RCO\ produces a low-level output pulse under those same conditions, but only while CLK is low. The counters can be cascaded easily by feeding RCO\ to CTEN\ of the succeeding counter if parallel clocking is used, or to CLK if parallel enabling is used. MAX/MIN can be used to accomplish look ahead for high-speed operation.

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類型 標題 日期
* Data sheet SN54HC191, SN74HC191 datasheet (Rev. D) 2003年 10月 2日
* SMD SN54HC191 SMD 5962-86891 2016年 6月 21日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 1996年 5月 1日
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

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CDIP (J) 16 檢視選項
LCCC (FK) 20 檢視選項

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