現在提供此產品的更新版本
功能相同，但引腳輸出與所比較的產品不同
SN65240
- Design to protect submicron 3-V or 5-V circuits from noise transients
- Port ESD protection capability exceeds:
- 15-kV human body model
- 2-kV machine model
- Available in a WCSP chip-scale package
- Stand-off voltage: 6 V (minimum)
- Low current leakage: 1-µA maximum at 6 V
- Low capacitance: 35-pF (typical)
The SN65220 device is a dual, and the SN65240 and SN75240 devices are quadruple, unidirectional transient voltage suppressors (TVS). These devices provide electrical noise transient protection to Universal Serial Bus (USB) low and full-speed ports. The input capacitance of 35 pF makes it unsuitable for high-speed USB 2.0 applications.
Any cabled I/O can be subjected to electrical noise transients from various sources. These noise transients can cause damage to the USB transceiver or the USB ASIC if they are of sufficient magnitude and duration.
The SN65220, SN65240, and SN75240 devices ESD performance is measured at the system level, according to IEC61000-4-2; system design, however, impacts the results of these tests. To accomplish a high compliance level, careful board design and layout techniques are required.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | SNx52x0 USB Port Transient Suppressors datasheet (Rev. J) | PDF | HTML | 2022年 8月 1日 |
| Application note | ESD and Surge Protection for USB Interfaces (Rev. B) | PDF | HTML | 2024年 1月 11日 | |
| Selection guide | System-Level ESD Protection Guide (Rev. D) | 2022年 9月 7日 | ||
| Application note | ESD Packaging and Layout Guide (Rev. B) | PDF | HTML | 2022年 8月 18日 | |
| User guide | Generic ESD Evaluation Module User's Guide (Rev. A) | PDF | HTML | 2021年 9月 27日 | |
| Analog Design Journal | Design Considerations for System-Level ESD Circuit Protection | 2012年 9月 25日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 引腳 | 下載 |
|---|---|---|
| PDIP (P) | 8 | 檢視選項 |
| TSSOP (PW) | 8 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。