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LVDS、M-LVDS 和 PECL IC

SN65EPT22

現行

3.3V 雙路 LVTTL/LVCMOS 至差動 LVPECL 緩衝器

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產品規格表

SN65EPT22

現行
產品規格表 立即訂購

產品詳細資料

Function Driver, Translator Protocols LVPECL Number of transmitters 2 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (MBits) 4000 Input signal CMOS, LVTTL Output signal LVPECL Rating Catalog Operating temperature range (°C) -40 to 85
Function Driver, Translator Protocols LVPECL Number of transmitters 2 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (MBits) 4000 Input signal CMOS, LVTTL Output signal LVPECL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6 VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • Dual 3.3V LVTTL to LVPECL Buffer
  • Operating Range
    • LVPECL VCC = 3.0 V to 3.6 V With
      GND = 0 V
  • Support for Clock Frequencies to 2.0 GHz (typ)
  • 420 ps Typical Propagation Delay
  • Deterministic HIGH Output Value for Open Input
    Conditions
  • Built-in Temperature Compensation
  • Drop in Compatible to MC100ELT23
  • PNP Single Ended Inputs for Minimal Loading
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion

All other trademarks are the property of their respective owners
  • Dual 3.3V LVTTL to LVPECL Buffer
  • Operating Range
    • LVPECL VCC = 3.0 V to 3.6 V With
      GND = 0 V
  • Support for Clock Frequencies to 2.0 GHz (typ)
  • 420 ps Typical Propagation Delay
  • Deterministic HIGH Output Value for Open Input
    Conditions
  • Built-in Temperature Compensation
  • Drop in Compatible to MC100ELT23
  • PNP Single Ended Inputs for Minimal Loading
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion

All other trademarks are the property of their respective owners

The SN65EPT22 is a low power dual LVTTL to LVPECL translator device. The device includes circuitry to maintain known logic HIGH level when inputs are in open condition. The SN65EPT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 package option.

The SN65EPT22 is a low power dual LVTTL to LVPECL translator device. The device includes circuitry to maintain known logic HIGH level when inputs are in open condition. The SN65EPT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 package option.
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技術文件

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類型 標題 日期
* Data sheet SN65EPT22 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer datasheet (Rev. B) PDF | HTML 2014年 11月 19日
Application note AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) 2007年 10月 17日

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模擬型號

SN65EPT22 IBIS Model

SLLM165.ZIP (13 KB) - IBIS Model
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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