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RS-485 & RS-422 收發器

SN65HVD10

現行

3.3 V 半雙工 RS-485 收發器，32Mbps

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產品規格表

SN65HVD10

現行
產品規格表 立即訂購

產品詳細資料

Number of receivers 1 Number of transmitters 1 Duplex Half Supply voltage (nom) (V) 3.3 Signaling rate (max) (MBits) 32 Fault protection (V) -9 to 14 Common-mode range (V) -7 to 12 Number of nodes 64 Isolated No Supply current (max) (µA) 15500 Rating Catalog Operating temperature range (°C) -40 to 125
Number of receivers 1 Number of transmitters 1 Duplex Half Supply voltage (nom) (V) 3.3 Signaling rate (max) (MBits) 32 Fault protection (V) -9 to 14 Common-mode range (V) -7 to 12 Number of nodes 64 Isolated No Supply current (max) (µA) 15500 Rating Catalog Operating temperature range (°C) -40 to 125
PDIP (P) 8 92.5083 mm² 9.81 x 9.43 SOIC (D) 8 29.4 mm² 4.9 x 6
  • Operates with a 3.3-V supply
  • Bus-pin ESD protection exceeds 16-kV HBM
  • 1/8 Unit-load option available (up to 256 nodes on the bus)
  • Optional driver output transition times for signaling rates (1)of 1 Mbps, 10 Mbps, and 32 Mbps
  • Meets or exceeds the requirements of ANSI TIA/EIA-485-A
  • Bus-pin short-circuit protection from –7 V to 12 V
  • Low-current standby mode: 1 µA, typical
  • Open-circuit, idle-bus, and shorted-bus fail-safe receiver
  • Thermal shutdown protection
  • Glitch-free power-up and power-down protection for hot-plugging applications
  • SN75176 footprint

(1)The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
  • Operates with a 3.3-V supply
  • Bus-pin ESD protection exceeds 16-kV HBM
  • 1/8 Unit-load option available (up to 256 nodes on the bus)
  • Optional driver output transition times for signaling rates (1)of 1 Mbps, 10 Mbps, and 32 Mbps
  • Meets or exceeds the requirements of ANSI TIA/EIA-485-A
  • Bus-pin short-circuit protection from –7 V to 12 V
  • Low-current standby mode: 1 µA, typical
  • Open-circuit, idle-bus, and shorted-bus fail-safe receiver
  • Thermal shutdown protection
  • Glitch-free power-up and power-down protection for hot-plugging applications
  • SN75176 footprint

(1)The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

The SN65HVD10, SN75HVD10, SN65HVD11, SN75HVD11, SN65HVD12, and SN75HVD12 bus transceivers all combine a 3-state differential line driver, as well as a differential input line receiver that operates with a single 3.3-V power supply. They are designed for balanced transmission lines and meet or exceed ANSI standard TIA/EIA-485-A and ISO 8482:1993. These differential bus transceivers are monolithic integrated circuits, designed for bidirectional data communication on multipoint bus-transmission lines. The drivers and receivers have active-high and active-low enables, that can be externally connected together to function as direction control. Very low device standby supply current, can be achieved by disabling the driver and the receiver.

The driver differential outputs and receiver differential inputs connect internally to form a differential input/output (I/O) bus port, that is designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. These parts feature wide positive and negative common-mode voltage ranges, making them suitable for party-line applications.

The SN65HVD10, SN75HVD10, SN65HVD11, SN75HVD11, SN65HVD12, and SN75HVD12 bus transceivers all combine a 3-state differential line driver, as well as a differential input line receiver that operates with a single 3.3-V power supply. They are designed for balanced transmission lines and meet or exceed ANSI standard TIA/EIA-485-A and ISO 8482:1993. These differential bus transceivers are monolithic integrated circuits, designed for bidirectional data communication on multipoint bus-transmission lines. The drivers and receivers have active-high and active-low enables, that can be externally connected together to function as direction control. Very low device standby supply current, can be achieved by disabling the driver and the receiver.

The driver differential outputs and receiver differential inputs connect internally to form a differential input/output (I/O) bus port, that is designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. These parts feature wide positive and negative common-mode voltage ranges, making them suitable for party-line applications.
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類型 標題 日期
* Data sheet SNx5HVD1x 3.3-V RS-485 Transceivers datasheet (Rev. P) PDF | HTML 2022年 2月 16日
EVM User's guide RS-485 Half-Duplex EVM User's Guide (Rev. C) PDF | HTML 2021年 9月 1日
Application note Operating RS-485 transceivers at fast signaling rates (Rev. A) 2019年 2月 6日
Application note The RS-485 Unit Load and Maximum Number of Bus Connections 2004年 3月 15日

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RS485-HF-DPLX-EVM — RS-485 半雙工評估模組

The RS-485 half-duplex evaluation module (EVM) helps designers evaluate device performance, supporting fast development and analysis of data-transmission systems using any of the SN65HVD1x, SN65HVD2x, SN65HVD7x, SN65HVD8x and SN65HVD96 half-duplex transceivers. The EVM board comes without the (...)
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SN65HVD10, SN75HVD10 IBIS Model (Rev. B)

SLLC114B.ZIP (5 KB) - IBIS Model
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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