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LVDS、M-LVDS 和 PECL IC

SN65LVDS2

現行

400-Mbps LVDS 單高速接收器

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產品規格表

SN65LVDS2

現行
產品規格表 立即訂購

產品詳細資料

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 1 Supply voltage (V) 2.5, 3.3 Signaling rate (Mbps) 400 Input signal LVDS Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 1 Supply voltage (V) 2.5, 3.3 Signaling rate (Mbps) 400 Input signal LVDS Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6 SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8
  • Meets or Exceeds the ANSI TIA/EIA-644 Standard
  • Designed for Signaling Rates (1) up to:
    • 630Mbps for Drivers
    • 400Mbps for Receivers
  • Operates From a 2.4V to 3.6V Supply
  • Available in SOT-23 and SOIC Packages
  • Bus-Terminal ESD Exceeds 9kV
  • Low-Voltage Differential Signaling With Typical Output Voltages of 350mV Into a 100Ω Load
  • Propagation Delay Times
    • 1.7ns Typical Driver
    • 2.5ns Typical Receiver
  • Power Dissipation at 200MHz
    • 25mW Typical Driver
    • 60mW Typical Receiver
  • LVDT Receiver Includes Line Termination
  • Low Voltage TTL (LVTTL) Level Driver Input Is 5V Tolerant
  • Driver Is Output High-Impedance with VCC < 1.5V
  • Receiver Output and Inputs are High-Impedance With VCC < 1.5V
  • Receiver Open-Circuit Fail Safe
  • Differential Input Voltage Threshold Less Than 100mV

(1)The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second)
  • Meets or Exceeds the ANSI TIA/EIA-644 Standard
  • Designed for Signaling Rates (1) up to:
    • 630Mbps for Drivers
    • 400Mbps for Receivers
  • Operates From a 2.4V to 3.6V Supply
  • Available in SOT-23 and SOIC Packages
  • Bus-Terminal ESD Exceeds 9kV
  • Low-Voltage Differential Signaling With Typical Output Voltages of 350mV Into a 100Ω Load
  • Propagation Delay Times
    • 1.7ns Typical Driver
    • 2.5ns Typical Receiver
  • Power Dissipation at 200MHz
    • 25mW Typical Driver
    • 60mW Typical Receiver
  • LVDT Receiver Includes Line Termination
  • Low Voltage TTL (LVTTL) Level Driver Input Is 5V Tolerant
  • Driver Is Output High-Impedance with VCC < 1.5V
  • Receiver Output and Inputs are High-Impedance With VCC < 1.5V
  • Receiver Open-Circuit Fail Safe
  • Differential Input Voltage Threshold Less Than 100mV

(1)The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second)

The SN65LVDS1, SN65LVDS2, and SN65LVDT2 devices are single, low-voltage, differential line drivers and receivers in the small-outline transistor package. The outputs comply with the TIA/EIA-644 standard and provide a minimum differential output voltage magnitude of 247mV into a 100Ω load at signaling rates up to 630Mbps for drivers and 400Mbps for receivers.

When the SN65LVDS1 device is used with an LVDS receiver (such as the SN65LVDT2) in a point-to-point connection, data or clocking signals can be transmitted over printed-circuit board traces or cables at very high rates with very low electromagnetic emissions and power consumption. The packaging, low power, low EMI, high ESD tolerance, and wide supply voltage range make the device ideal for battery-powered applications.

The SN65LVDS1, SN65LVDS2, and SN65LVDT2 devices are characterized for operation from –40°C to 85°C.

The SN65LVDS1, SN65LVDS2, and SN65LVDT2 devices are single, low-voltage, differential line drivers and receivers in the small-outline transistor package. The outputs comply with the TIA/EIA-644 standard and provide a minimum differential output voltage magnitude of 247mV into a 100Ω load at signaling rates up to 630Mbps for drivers and 400Mbps for receivers.

When the SN65LVDS1 device is used with an LVDS receiver (such as the SN65LVDT2) in a point-to-point connection, data or clocking signals can be transmitted over printed-circuit board traces or cables at very high rates with very low electromagnetic emissions and power consumption. The packaging, low power, low EMI, high ESD tolerance, and wide supply voltage range make the device ideal for battery-powered applications.

The SN65LVDS1, SN65LVDS2, and SN65LVDT2 devices are characterized for operation from –40°C to 85°C.
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技術文件

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類型 標題 日期
* Data sheet SN65LVDxx High-Speed Differential Line Drivers and Receivers datasheet (Rev. M) PDF | HTML 2024年 3月 1日
Application brief LVDS to Improve EMC in Motor Drives 2018年 9月 27日
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 2018年 8月 3日
Application brief How to Terminate LVDS Connections with DC and AC Coupling 2018年 5月 16日
Application note An Overview of LVDS Technology 1998年 10月 5日

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模擬型號

SN65LVDS2 IBIS Model (Rev. A)

SLLC021A.ZIP (201 KB) - IBIS Model
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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SOIC (D) 8 Ultra Librarian
SOT-23 (DBV) 5 Ultra Librarian
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