首頁 介面 LVDS、M-LVDS 和 PECL IC
首頁
介面
LVDS、M-LVDS 和 PECL IC

SN65LVDS250

現行

2.0-Gbps 4x4 交叉點交換器

立即訂購
產品規格表

SN65LVDS250

現行
產品規格表 立即訂購

產品詳細資料

Function Crosspoint Protocols LVDS Number of transmitters 4 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (MBits) 2000 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Crosspoint Protocols LVDS Number of transmitters 4 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (MBits) 2000 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DBT) 38 62.08 mm² 9.7 x 6.4
  • Greater Than 2.0 Gbps Operation
  • Nonblocking Architecture Allows Each Output to be Connected to Any Input
  • Pk.Pk Jitter:
    • 60 ps Typical at 2.0 Gbps
    • 110 ps Typical at 2.5 Gbps
  • Compatible With ANSI TIA/EIA-644-A LVDS Standard
  • Available Packaging 38-Pin TSSOP
  • 25 mV of Input Voltage Threshold Hysteresis
  • Propagation Delay Times: 800 ps Typical
  • Inputs Electrically Compatible With LVPECL, CML and LVDS Signal Levels
  • Operates From a Single 3.3-V Supply
  • Low Power: 110 mA Typical
  • Integrated 110- Line Termination Resistors Available With SN65LVDT250
  • APPLICATIONS
    • Clock Buffering/Clock Muxing
    • Wireless Base Stations
    • High-Speed Network Routing
    • Telecom/Datacom
  • Greater Than 2.0 Gbps Operation
  • Nonblocking Architecture Allows Each Output to be Connected to Any Input
  • Pk.Pk Jitter:
    • 60 ps Typical at 2.0 Gbps
    • 110 ps Typical at 2.5 Gbps
  • Compatible With ANSI TIA/EIA-644-A LVDS Standard
  • Available Packaging 38-Pin TSSOP
  • 25 mV of Input Voltage Threshold Hysteresis
  • Propagation Delay Times: 800 ps Typical
  • Inputs Electrically Compatible With LVPECL, CML and LVDS Signal Levels
  • Operates From a Single 3.3-V Supply
  • Low Power: 110 mA Typical
  • Integrated 110- Line Termination Resistors Available With SN65LVDT250
  • APPLICATIONS
    • Clock Buffering/Clock Muxing
    • Wireless Base Stations
    • High-Speed Network Routing
    • Telecom/Datacom

The SN65LVDS250 and SN65LVDT250 are 4x4 nonblocking crosspoint switches in a flow-through pin-out allowing for ease in PCB layout. Low-voltage differential signaling (LVDS) is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve the high signaling speeds while maintaining low signal skews. The SN65LVDT250 incorporates 110- termination resistors for those applications where board space is a premium.

The SN65LVDS250 and SN65LVDT250 are characterized for operation from –40°C to 85°C.

The SN65LVDS250 and SN65LVDT250 are 4x4 nonblocking crosspoint switches in a flow-through pin-out allowing for ease in PCB layout. Low-voltage differential signaling (LVDS) is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve the high signaling speeds while maintaining low signal skews. The SN65LVDT250 incorporates 110- termination resistors for those applications where board space is a premium.

The SN65LVDS250 and SN65LVDT250 are characterized for operation from –40°C to 85°C.
open-in-new 尋找其它 LVDS、M-LVDS 和 PECL IC
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 2
類型 標題 日期
* Data sheet SN65LVDS250, SN65LVDT250: LVDS 4X4 Crosspoint Switch datasheet (Rev. B) 2004年 10月 14日
EVM User's guide 4x4 Crosspoint Switch EVM User's Guide (Rev. A) 2004年 1月 29日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

SN65LVDS125AEVM — SN65LVDS125 評估模組

The SN65LVDS125A is a 4 x 4 non-blocking cross point switch. Low-Voltage differential signaling (LVDS) is used to achieve signaling rates of 1.5 Gbps per channel. Each output driver includes a 4:1 multiplexer to allow any input to be routed to any output.Internal signal paths are fully differential (...)

使用指南: PDF
TI.com 無法提供
模擬型號

SN65LVDS250 IBIS Model

SLLC214.ZIP (11 KB) - IBIS Model
下載
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
要求
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
檢視選項
封裝 引腳 下載
TSSOP (DBT) 38 檢視選項
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 資格摘要
  • 進行中可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片