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SN74ABT162244

現行

具有 TTL 相容 CMOS 輸入和 3 態輸出的 16 通道、4.5-V 至 5.5-V 緩衝器

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產品規格表

SN74ABT162244

現行
產品規格表 立即訂購

產品詳細資料

Technology family ABT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 16 IOL (max) (mA) 12 Supply current (max) (µA) 30000 IOH (max) (mA) -12 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Damping resistors, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family ABT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 16 IOL (max) (mA) 12 Supply current (max) (µA) 30000 IOH (max) (mA) -12 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Damping resistors, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1 TVSOP (DGV) 48 62.08 mm² 9.7 x 6.4
  • Members of the Texas Instruments Widebus™ Family
  • Output Ports Have Equivalent 25- Series Resistors, So No External Resistors Are Required
  • Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per JESD-17

Widebus is a trademark of Texas Instruments.
  • Members of the Texas Instruments Widebus™ Family
  • Output Ports Have Equivalent 25- Series Resistors, So No External Resistors Are Required
  • Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per JESD-17

Widebus is a trademark of Texas Instruments.

The ’ABT162244 devices are 16-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide noninverting outputs and symmetrical active-low output-enable (OE)\ inputs.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The ’ABT162244 devices are 16-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide noninverting outputs and symmetrical active-low output-enable (OE)\ inputs.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
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類型 標題 日期
* Data sheet SN54ABT162244, SN74ABT162244 datasheet (Rev. E) 2004年 6月 3日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
Application note Quad Flatpack No-Lead Logic Packages (Rev. D) 2004年 2月 16日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
Selection guide Advanced Bus Interface Logic Selection Guide 2001年 1月 9日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) 1997年 3月 1日
Application note Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) 1996年 12月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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模擬型號

HSPICE Model for SN74ABT162244

SCBM098.ZIP (128 KB) - HSpice Model
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模擬型號

SN74ABT162244 Behavioral SPICE Model

SCBM155.ZIP (7 KB) - PSpice Model
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模擬型號

SN74ABT162244 IBIS Model (Rev. C)

SCBM003C.ZIP (15 KB) - IBIS Model
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封裝 引腳 下載
SSOP (DL) 48 檢視選項
TSSOP (DGG) 48 檢視選項
TVSOP (DGV) 48 檢視選項
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