產品詳細資料

Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 2.7 Number of channels 1 IOL (max) (mA) 9 IOH (max) (mA) -9 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Technology family AUC Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 2.7 Number of channels 1 IOL (max) (mA) 9 IOH (max) (mA) -9 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Technology family AUC Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YZP) 5 2.1875 mm² 1.75 x 1.25 SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-5X3 (DRL) 5 2.56 mm² 1.6 x 1.6 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree™ Package
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial Power Down Mode and Back Drive Protection
  • Sub-1-V Operable
  • Max tpd of 2.2 ns at 1.8 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±8-mA Output Drive at 1.8 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree™ Package
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial Power Down Mode and Back Drive Protection
  • Sub-1-V Operable
  • Max tpd of 2.2 ns at 1.8 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±8-mA Output Drive at 1.8 V

This single inverter gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC1G04 performs the Boolean function Y = A.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the ouput, preventing damaging current backflow through the device when it is powered down.

For more information about AUC Little Logic devices, see Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, SCEA027.

This single inverter gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC1G04 performs the Boolean function Y = A.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the ouput, preventing damaging current backflow through the device when it is powered down.

For more information about AUC Little Logic devices, see Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, SCEA027.

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SN74AUP1G04 現行 單路 0.8-V 至 3.6-V 低功耗逆變器 Larger voltage range (0.8V to 3.6V), lower average drive strength (4mA)

技術文件

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類型 標題 日期
* Data sheet SN74AUC1G04 Single Inverter Gate datasheet (Rev. R) PDF | HTML 2017年 6月 8日
Selection guide Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note How to Select Little Logic (Rev. A) 2016年 7月 26日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004年 11月 4日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus Devices 2003年 3月 21日
User guide AUC Data Book, January 2003 (Rev. A) 2003年 1月 1日
Application note Texas Instruments Little Logic Application Report 2002年 11月 1日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002年 3月 27日
More literature AUC Product Brochure (Rev. A) 2002年 3月 18日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南: PDF
TI.com 無法提供
模擬型號

HSPICE Model of SN74AUC1G04 (Rev. A)

SCEJ128A.ZIP (91 KB) - HSpice Model
模擬型號

SN74AUC1G04 Behavioral SPICE Model

SCEM729.ZIP (7 KB) - PSpice Model
模擬型號

SN74AUC1G04 IBIS Model (Rev. B)

SCEM217B.ZIP (55 KB) - IBIS Model
參考設計

TIDM-RF430FRLSENSE — RF430FRL152H NFC 溫度及燈光感測器參考設計

This reference design provides a platform to evaluate the RF430FRL152H NFC Sensor Interface Transponder.  Directly out of the box, thermistor and photo transistor measurements can be communicated to an NFC enabled smart phone or other NFC/RFID Reader device.  This reference design can be (...)
電路圖: PDF
封裝 引腳 下載
DSBGA (YZP) 5 檢視選項
SOT-23 (DBV) 5 檢視選項
SOT-5X3 (DRL) 5 檢視選項
SOT-SC70 (DCK) 5 檢視選項
USON (DRY) 6 檢視選項

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