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固定方向電壓轉換器

SN74AVC2T244

現行

雙位元雙電源匯流排收發器

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產品規格表

SN74AVC2T244

現行
產品規格表 立即訂購

產品詳細資料

Technology family AVC Bits (#) 2 Configuration 2 Ch A to B 0 Ch B to A High input voltage (min) (V) 0.81 High input voltage (max) (V) 3.6 Vout (min) (V) 3000 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -24 IOL (max) (mA) -24 Supply current (max) (µA) 3.6 Features 1.4, 2.16 Input type Standard CMOS Output type 3-State, Balanced CMOS Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AVC Bits (#) 2 Configuration 2 Ch A to B 0 Ch B to A High input voltage (min) (V) 0.81 High input voltage (max) (V) 3.6 Vout (min) (V) 3000 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -24 IOL (max) (mA) -24 Supply current (max) (µA) 3.6 Features 1.4, 2.16 Input type Standard CMOS Output type 3-State, Balanced CMOS Rating Catalog Operating temperature range (°C) -40 to 85
X2SON (DQE) 8 1.4 mm² 1.4 x 1 X2SON (DQM) 8 2.16 mm² 1.8 x 1.2
  • Wide Operating VCC Range of 0.9 V to 3.6 V
  • Low Static-Power Consumption, 6-µA Max ICC
  • Output Enable Feature Allows User to Disable Outputs to Reduce Power Consumption
  • ±24-mA Output Drive at 3.0 V
  • Ioff Supports Partial Power-Down-Mode Operation
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
  • Maximum Data Rates
    • 380 Mbps (1.8-V to 3.3-V Translation)
    • 200 Mbps (<1.8-V to 3.3-V Translation)
    • 200 Mbps (Translate to 2.5 V or 1.8 V)
    • 150 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 5000-V Human-Body Model (A114-A)
  • Wide Operating VCC Range of 0.9 V to 3.6 V
  • Low Static-Power Consumption, 6-µA Max ICC
  • Output Enable Feature Allows User to Disable Outputs to Reduce Power Consumption
  • ±24-mA Output Drive at 3.0 V
  • Ioff Supports Partial Power-Down-Mode Operation
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
  • Maximum Data Rates
    • 380 Mbps (1.8-V to 3.3-V Translation)
    • 200 Mbps (<1.8-V to 3.3-V Translation)
    • 200 Mbps (Translate to 2.5 V or 1.8 V)
    • 150 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 5000-V Human-Body Model (A114-A)

This 2-bit unidirectional translator uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 0.9 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 0.9 V to 3.6 V. This allows for low-voltage translation between 0.9-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V and 3.6-V voltage nodes. For the SN74AVC2T244, when the output-enable ( OE) input is high, all outputs are placed in the high-impedance state. The SN74AVC2T244 is designed so that the OE input circuit is referenced to VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This 2-bit unidirectional translator uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 0.9 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 0.9 V to 3.6 V. This allows for low-voltage translation between 0.9-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V and 3.6-V voltage nodes. For the SN74AVC2T244, when the output-enable ( OE) input is high, all outputs are placed in the high-impedance state. The SN74AVC2T244 is designed so that the OE input circuit is referenced to VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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類型 標題 日期
* Data sheet SN74AVC2T244 2-Bit Unidirectional Voltage-level Translator datasheet (Rev. C) PDF | HTML 2021年 3月 12日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
EVM User's guide SN74AVC2T244EVM 2011年 9月 19日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
More literature LCD Module Interface Application Clip 2003年 5月 9日
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002年 8月 20日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999年 7月 7日
Application note AVC Logic Family Technology and Applications (Rev. A) 1998年 8月 26日

設計與開發

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開發板

SN74AVC2T244EVM — SN74AVC2T244 評估模組

The SN74AVC2T244 is a 2-bit voltage level translator. This translator is a single direction voltage translator, with OE. When the output-enable (OE) input is high, all outputs are placed in the high-impedance state. The A port is designed to track VCCA. VCCA accepts any supply voltage from 0.9V to (...)

使用指南: PDF
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開發板

TAS6424EQ1EVM — TAS6424E-Q1 評估模組 75-W、2-MHz、四通道數位輸入 D 級音訊放大器

TAS6424EQ1EVM 評估模組 (EVM) 展示適合車載資訊娛樂系統的 TAS6424E-Q1、A 2.1-MHz，四通道數位輸入 D 類音訊放大器解決方案。2.1-Mhz 切換頻率可大幅縮減電感器尺寸。TAS6424E-Q1 為每通道提供 25 W (10% THD+N) 至 4-Ω，配備 14.4-V 供電與整合 I2C 診斷與保護。TAS6424E-Q1 包含展頻技術，符合 CISPR25 Class 5 EMI 規範標準。
使用指南: PDF | HTML
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模擬型號

SN74AVC2T244 IBIS Model

SCEM543.ZIP (55 KB) - IBIS Model
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參考設計

TIDEP0025 — 適用於工業通訊和馬達控制的單晶片驅動

This reference design implements hardware interface based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The platform also allows you to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables designs with a low (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0022 — 具有整合式 BiSS C 主介面的 ARM MPU 參考設計

Implementation of BiSS C Master protocol on Industrial Communication Sub-System (PRU-ICSS). The design provides full documentation and source code for Programmable Realtime Unit (PRU).
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0035 — 具有整合式 HIPERFACE DSL 主介面的 ARM MPU 參考設計

This reference design implements HIPERFACE DSL master protocol on Industrial Communication Sub-System (PRU-ICSS). The two-wire interface allows integration of position feedback wires into motor cable.  It consists of AM437x PRU-ICSS firmware and TIDA-00177 transceiver reference design.
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0050 — EnDat 2.2 系統參考設計

This reference design implements EnDat 2.2 Master protocol stack and hardware interface based on HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of EnDat 2.2 Master protocol stack, half-duplex communications using RS-485 transceivers and the line termination (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP-0075 — 工業通訊閘道 PROFINET IRT 轉 PROFIBUS 主站參考設計

PROFINET is becoming the leading industrial Ethernet protocol in automation due to its high-speed, deterministic communications and enterprise connectivity. However, as the world’s most popular fieldbus, PROFIBUS’s importance and usage will continue for many years due to legacy (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0078 — 適用於 AM572x 的 OPC UA 資料存取伺服器參考設計

OPC UA is an industrial machine-to-machine protocol designed to allow interoperability and communication between all machines connected under Industry 4.0. This reference design demonstrates use of the Matrikon OPC™ OPC UA server development kit (SDK) to allow communications using an OPC UA (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01572 — 數位輸入、D 類、IV 感測音訊放大器的立體聲評估模組參考設計

This reference design provides a high-performance stereo audio subsystem for use in PC applications. It operates off a single supply, ranging from 4.5 V to 16 V, and features the TAS2770, a digital-input Class-D audio amplifier that provides excellent noise and distortion performance and is (...)
Design guide: PDF
電路圖: PDF
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