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電壓轉換器及電平移位器
方向控制電壓轉換器

SN74AVCB164245-EP

現行

具可配置轉換和 3 狀態輸出的強化型產品 16 位元雙電源匯流排收發器

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SN74AVCB164245-EP

現行
產品規格表 立即訂購

產品詳細資料

Technology family AVC Bits (#) 16 High input voltage (min) (V) 0.91 High input voltage (max) (V) 3.6 Vout (min) (V) 1.4 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 80 Features Output damping resistors, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Technology family AVC Bits (#) 16 High input voltage (min) (V) 0.91 High input voltage (max) (V) 3.6 Vout (min) (V) 1.4 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 80 Features Output damping resistors, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • Member of the Texas Instruments Widebus Family
  • DOC Circuitry Dynamically Changes Output Impedance,
    Resulting in Noise Reduction Without Speed Degradation
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With
    IOH and IOL of ±24 mA at 2.5-V
    VCC
  • Control Inputs VIH and VIL Levels Are
    Referenced to VCCB Voltage
  • If Either VCC Input Is at GND, Both Ports Are in the
    High-Impedance State
  • Overvoltage-Tolerant Inputs and Outputs Allow Mixed-Voltage-Mode Data
    Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over
    Full 1.4-V to 3.6-V Power-Supply Range
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 750-V Charged-Device Model (C101)
  • Member of the Texas Instruments Widebus Family
  • DOC Circuitry Dynamically Changes Output Impedance,
    Resulting in Noise Reduction Without Speed Degradation
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With
    IOH and IOL of ±24 mA at 2.5-V
    VCC
  • Control Inputs VIH and VIL Levels Are
    Referenced to VCCB Voltage
  • If Either VCC Input Is at GND, Both Ports Are in the
    High-Impedance State
  • Overvoltage-Tolerant Inputs and Outputs Allow Mixed-Voltage-Mode Data
    Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over
    Full 1.4-V to 3.6-V Power-Supply Range
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 750-V Charged-Device Model (C101)

This 16-bit (dual-octal) noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.4 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCB164245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVCB164245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCB.

To ensure the high-impedance state during power up or power down, OE should be tied to VCCB through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. If either VCC input is at GND, both ports are in the high-impedance state.

This 16-bit (dual-octal) noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.4 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCB164245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVCB164245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCB.

To ensure the high-impedance state during power up or power down, OE should be tied to VCCB through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. If either VCC input is at GND, both ports are in the high-impedance state.
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類型 標題 日期
* Data sheet SN74AVCB164245-EP 16-Bit Dual-Supply Bus Transceiver datasheet (Rev. A) 2013年 2月 12日
* Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
* VID SN74AVCB164245-EP VID V6213602 2016年 6月 21日
* Radiation & reliability report CAVCB164245MDGGREP Reliability Report 2013年 4月 24日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
More literature LCD Module Interface Application Clip 2003年 5月 9日
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002年 8月 20日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999年 7月 7日
Application note AVC Logic Family Technology and Applications (Rev. A) 1998年 8月 26日

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