產品詳細資料

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -12 Input type TTL Output type TTL Features Very high speed (tpd 5-10ns) Technology family F Rating Catalog Operating temperature range (°C) 0 to 70
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -12 Input type TTL Output type TTL Features Very high speed (tpd 5-10ns) Technology family F Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • Combines ´F245 and ´F280B Functions in One Package
  • High-Impedance N-P-N Inputs for Reduced Loading (70 uA in Low and High States)
  • High Output Drive and Light Bus Loading
  • 3-State B Outputs Sink 64 mA and Source 15 mA
  • Input Diodes for Termination Effects
  • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

 

  • Combines ´F245 and ´F280B Functions in One Package
  • High-Impedance N-P-N Inputs for Reduced Loading (70 uA in Low and High States)
  • High Output Drive and Light Bus Loading
  • 3-State B Outputs Sink 64 mA and Source 15 mA
  • Input Diodes for Termination Effects
  • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

 

The SN74F657 contains eight noninverting buffers with 3-state outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a specified current sinking capability of 24 mA at the A port and 64 mA at the B port.

The transmit/receive (T/R\) input determines the direction of the data flow through the bidirectional transceivers. When T/R\ is high, data is transmitted from the A port to the B port. When T/R\ is low, data is received at the A port from the B port.

When the output enable () input is high, both the A and B ports are placed in a high-impedance state (disabled). The ODD/EVEN\ input allows the user to select between odd or even parity systems. When transmitting from A port to B port (T/R\ high), PARITY is an output from the generator/checker. When receiving from B port to A port (T/R\ low), PARITY is an input.

When transmitting (T/R\ high), the parity select (ODD/EVEN\) input is made high or low as appropriate. The A port is then polled to determine the number of high bits.The PARITY output goes to the logic state determined by ODD/EVEN\ and the number of high bits on A port. When ODD/EVEN\ is low (for even parity) and the number of high bits on A port is odd, the PARITY will be high, transmitting even parity. If the number of high bits on A port is even, the PARITY will be low, keeping even parity.

When in the receive mode (T/R\ low), the B port is polled to determine the number of high bits. If ODD/EVEN\ is low (for even parity) and the number of highs on B port is:

  1. 1. Odd and the PARITY input is high, then ERR\ will be high signifying no error.
  2. 2. Even and the PARITY input is high, then ERR\ will be low indicating an error.

The SN74F657 is characterized for operation from 0°C to 70°C.

 

 

The SN74F657 contains eight noninverting buffers with 3-state outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a specified current sinking capability of 24 mA at the A port and 64 mA at the B port.

The transmit/receive (T/R\) input determines the direction of the data flow through the bidirectional transceivers. When T/R\ is high, data is transmitted from the A port to the B port. When T/R\ is low, data is received at the A port from the B port.

When the output enable () input is high, both the A and B ports are placed in a high-impedance state (disabled). The ODD/EVEN\ input allows the user to select between odd or even parity systems. When transmitting from A port to B port (T/R\ high), PARITY is an output from the generator/checker. When receiving from B port to A port (T/R\ low), PARITY is an input.

When transmitting (T/R\ high), the parity select (ODD/EVEN\) input is made high or low as appropriate. The A port is then polled to determine the number of high bits.The PARITY output goes to the logic state determined by ODD/EVEN\ and the number of high bits on A port. When ODD/EVEN\ is low (for even parity) and the number of high bits on A port is odd, the PARITY will be high, transmitting even parity. If the number of high bits on A port is even, the PARITY will be low, keeping even parity.

When in the receive mode (T/R\ low), the B port is polled to determine the number of high bits. If ODD/EVEN\ is low (for even parity) and the number of highs on B port is:

  1. 1. Odd and the PARITY input is high, then ERR\ will be high signifying no error.
  2. 2. Even and the PARITY input is high, then ERR\ will be low indicating an error.

The SN74F657 is characterized for operation from 0°C to 70°C.

 

 

下載 觀看有字幕稿的影片 影片

您可能會感興趣的類似產品

open-in-new 比較替代產品
引腳對引腳的功能與所比較的產品相同
CD74ACT245 現行 具有 3 態輸出的八路非反相匯流排收發器 Higher average drive strength (24mA)

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 9
類型 標題 日期
* Data sheet Octal Transceiver With Parity Generator/Checker And 3-State Outputs datasheet (Rev. A) 1993年 10月 1日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML
TI.com 無法提供
封裝 引腳 下載
SOIC (DW) 24 檢視選項

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 資格摘要
  • 進行中可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片