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電壓轉換器及電平移位器
特定應用電壓轉換器

SN74FB1653

現行

具有緩衝時鐘線路的 17 位 LVTTL/BTL 通用儲存收發器

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產品規格表

SN74FB1653

現行
產品規格表 立即訂購

產品詳細資料

Technology family FB Applications GTL Rating Catalog Operating temperature range (°C) 0 to 70
Technology family FB Applications GTL Rating Catalog Operating temperature range (°C) 0 to 70
HLQFP (PCA) 100 256 mm² 16 x 16
  • Compatible With IEEE Std 1194.1-1991 (BTL)
  • LVTTL A Port, Backplane Transceiver Logic (BTL) B\ Port
  • Open-Collector B\-Port Outputs Sink 100 mA
  • B\-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage
  • High-Impedance State During Power Up and Power Down
  • Selectable Clock Delay
  • TTL-Input Structures Incorporate Active Clamping Networks to Aid in Line Termination
  • BIAS VCC Minimizes Signal Distortion During Live Insertion/Withdrawal
  • Compatible With IEEE Std 1194.1-1991 (BTL)
  • LVTTL A Port, Backplane Transceiver Logic (BTL) B\ Port
  • Open-Collector B\-Port Outputs Sink 100 mA
  • B\-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage
  • High-Impedance State During Power Up and Power Down
  • Selectable Clock Delay
  • TTL-Input Structures Incorporate Active Clamping Networks to Aid in Line Termination
  • BIAS VCC Minimizes Signal Distortion During Live Insertion/Withdrawal

The SN74FB1653 contains an 8-bit and a 9-bit transceiver with a buffered clock. The clock and transceivers are designed to translate signals between LVTTL and BTL environments. The device is designed specifically to be compatible with IEEE Std 1194.1-1991 (BTL).

The A port operates at LVTTL signal levels. The A outputs reflect the inverse of the data at the B\ port when the A-port output enable (OEA) is high. When OEA is low or when VCC(5 V) typically is less than 2.5 V, the A outputs are in the high-impedance state.

The B\ port operates at BTL signal levels. The open-collector B\ ports are specified to sink 100 mA. Two output enables (OEB and OEB)\ are provided for the B\ outputs. When OEB is low, OEB\ is high, or VCC(5 V) typically is less than 2.5 V, the B port is turned off.

The clock-select (2SEL1 and 2SEL2) inputs are used to configure the TTL-to-BTL clock paths and delays (refer to the MUX-MODE DELAY table).

BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC(5 V) is not connected.

BG VCC and BG GND are the supply inputs for the bias generator.

VREF is an internally generated voltage source. It is recommended that VREF be decoupled with a 0.1-µF capacitor.

Enhanced heat-dissipation techniques should be used when operating this device from AI to A0 at frequencies greater than 50 MHz, or from AI to B\ or B\ to A0 at frequencies greater than 100 MHz.

The SN74FB1653 contains an 8-bit and a 9-bit transceiver with a buffered clock. The clock and transceivers are designed to translate signals between LVTTL and BTL environments. The device is designed specifically to be compatible with IEEE Std 1194.1-1991 (BTL).

The A port operates at LVTTL signal levels. The A outputs reflect the inverse of the data at the B\ port when the A-port output enable (OEA) is high. When OEA is low or when VCC(5 V) typically is less than 2.5 V, the A outputs are in the high-impedance state.

The B\ port operates at BTL signal levels. The open-collector B\ ports are specified to sink 100 mA. Two output enables (OEB and OEB)\ are provided for the B\ outputs. When OEB is low, OEB\ is high, or VCC(5 V) typically is less than 2.5 V, the B port is turned off.

The clock-select (2SEL1 and 2SEL2) inputs are used to configure the TTL-to-BTL clock paths and delays (refer to the MUX-MODE DELAY table).

BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC(5 V) is not connected.

BG VCC and BG GND are the supply inputs for the bias generator.

VREF is an internally generated voltage source. It is recommended that VREF be decoupled with a 0.1-µF capacitor.

Enhanced heat-dissipation techniques should be used when operating this device from AI to A0 at frequencies greater than 50 MHz, or from AI to B\ or B\ to A0 at frequencies greater than 100 MHz.
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類型 標題 日期
* Data sheet SN74FB1653 datasheet (Rev. H) 2004年 3月 10日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
Selection guide Advanced Bus Interface Logic Selection Guide 2001年 1月 9日
Application note GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A) 1997年 3月 1日
Application note Next-Generation BTL/Futurebus Transceivers Allow Single-Sided SMT Manufacturing (Rev. C) 1997年 3月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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模擬型號

SN74FB1653 IBIS Model (Rev. C)

SCBM012C.ZIP (26 KB) - IBIS Model
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