產品詳細資料

Configuration Serial-in, Parallel-out Bits (#) 8 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 65 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
Configuration Serial-in, Parallel-out Bits (#) 8 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 65 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4 VQFN (RGY) 14 12.25 mm² 3.5 x 3.5 WQFN (BQA) 14 7.5 mm² 3 x 2.5
  • V CC operation of 2 V to 5.5 V
  • Maximum t pd of 10.5 ns at 5 V
  • Typical V OLP (output ground bounce) < 0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (output V OH undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
  • Ioff supports live insertion, partial power-down mode, and back-drive protection
  • Support mixed-mode voltage operation on all ports
  • Latch-up performance exceeds 250 mA per JESD 17
  • V CC operation of 2 V to 5.5 V
  • Maximum t pd of 10.5 ns at 5 V
  • Typical V OLP (output ground bounce) < 0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (output V OH undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
  • Ioff supports live insertion, partial power-down mode, and back-drive protection
  • Support mixed-mode voltage operation on all ports
  • Latch-up performance exceeds 250 mA per JESD 17

The SN74LV164A devices are 8-bit parallel-out serial shift registers designed for 2 V to 5.5 V V CC operation.

The SN74LV164A devices are 8-bit parallel-out serial shift registers designed for 2 V to 5.5 V V CC operation.

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類型 標題 日期
* Data sheet SN74LV164A 8-Bit Parallel-Out Serial Shift Registers datasheet (Rev. K) PDF | HTML 2023年 3月 24日
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
Design guide EMC Compatible Automotive LED Rear Lamp Sequential-Turn Animation Design Guide 2016年 6月 2日

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14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

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14-24-NL-LOGIC-EVM — 適用於 14 針腳至 24 針腳無引線封裝的邏輯產品通用評估模組

14-24-NL-LOGIC-EVM 是一款靈活的評估模組 (EVM),設計用途可支援任何具有 14 針腳至 24 針腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的邏輯或轉換裝置。

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模擬型號

SN74LV164A IBIS Model

SCEM131.ZIP (16 KB) - IBIS Model
參考設計

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電路圖: PDF
參考設計

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This design is an analog solution for automotive rear lamps with sequential turn animations. This design is compatible with the TL81000 RI and the BCI test in a third-party EMC lab. This design also illustrates full automotive diagnostic with low quiescent current during fault mode.
Design guide: PDF
電路圖: PDF
參考設計

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Design guide: PDF
電路圖: PDF
封裝 引腳 下載
SOIC (D) 14 檢視選項
SOP (NS) 14 檢視選項
SSOP (DB) 14 檢視選項
TSSOP (PW) 14 檢視選項
TVSOP (DGV) 14 檢視選項
VQFN (RGY) 14 檢視選項
WQFN (BQA) 14 檢視選項

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