產品詳細資料

Configuration 1:1 SPST Number of channels 2 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5 Protocols Analog Ron (typ) (Ω) 6 CON (typ) (pF) 14 ON-state leakage current (max) (µA) 1 Supply current (typ) (µA) 1 Bandwidth (MHz) 300 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 50 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
Configuration 1:1 SPST Number of channels 2 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5 Protocols Analog Ron (typ) (Ω) 6 CON (typ) (pF) 14 ON-state leakage current (max) (µA) 1 Supply current (typ) (µA) 1 Bandwidth (MHz) 300 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 50 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25 SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Available in the Texas Instruments
    NanoFree™ Package
  • 1.65-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 0.8 ns at 3.3 V
  • High On-Off Output Voltage Ratio
  • High Degree of Linearity
  • High Speed, Typically 0.5 ns
    (VCC = 3 V, CL = 50 pF)
  • Rail-to-Rail Input/Output
  • Low ON-State Resistance, Typically ≉6 Ω
    (VCC = 4.5 V)
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • Available in the Texas Instruments
    NanoFree™ Package
  • 1.65-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 0.8 ns at 3.3 V
  • High On-Off Output Voltage Ratio
  • High Degree of Linearity
  • High Speed, Typically 0.5 ns
    (VCC = 3 V, CL = 50 pF)
  • Rail-to-Rail Input/Output
  • Low ON-State Resistance, Typically ≉6 Ω
    (VCC = 4.5 V)
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II

This dual bilateral analog switch is designed for
1.65-V to 5.5-V VCC operation.

The SN74LVC2G66 device can handle both analog and digital signals. The SN74LVC2G66 device permits signals with amplitudes of up to 5.5 V (peak) to be transmitted in either direction.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Each switch section has its own enable-input control (C). A high-level voltage applied to C turns on the associated switch section.

Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.

This dual bilateral analog switch is designed for
1.65-V to 5.5-V VCC operation.

The SN74LVC2G66 device can handle both analog and digital signals. The SN74LVC2G66 device permits signals with amplitudes of up to 5.5 V (peak) to be transmitted in either direction.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Each switch section has its own enable-input control (C). A high-level voltage applied to C turns on the associated switch section.

Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.

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類型 標題 日期
* Data sheet SN74LVC2G66 Dual Bilateral Analog Switch datasheet (Rev. N) PDF | HTML 2018年 8月 20日
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022年 6月 2日
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021年 12月 1日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note How to Select Little Logic (Rev. A) 2016年 7月 26日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004年 11月 4日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003年 11月 6日
More literature I2C and Serial Bus Devices Application Clip 2003年 7月 10日
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002年 12月 18日
Application note Texas Instruments Little Logic Application Report 2002年 11月 1日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002年 3月 27日
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note LVC Characterization Information 1996年 12月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996年 9月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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開發板

DIP-ADAPTER-EVM — DIP 轉接器評估模組

Speed up your op amp prototyping and testing with the DIP-Adapter-EVM, which provides a fast, easy and inexpensive way to interface with small, surface-mount ICs. You can connect any supported op amp using the included Samtec terminal strips or wire them directly to existing circuits.

The (...)

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介面轉接器

LEADED-ADAPTER1 — 適用於快速測試 TI 的 5、8、10、16 及 24 針腳引線封裝的表面貼裝至 DIP 接頭適配器

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

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LEADLESS-ADAPTER1 — 用於測試 TI 的 6、8、10、12、14、16 和 20 針腳無引線封裝的表面貼裝至 DIP 接頭適配器

The EVM-LEADLESS1 board allows for quick testing and bread boarding of TI's common leadless packages.  The board has footprints to convert TI's DRC, DTP, DQE, RBW, RGY, RSE, RSV, RSW RTE, RTJ, RUK , RUC, RUG, RUM,RUT and YZP surface mount packages to 100mil DIP headers.
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模擬型號

HSPICE Model for SN74LVC2G66

SCEJ257.ZIP (87 KB) - HSpice Model
模擬型號

SN74LVC2G66 IBIS Model

SCEM446.ZIP (34 KB) - IBIS Model
參考設計

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This reference design implements a cost-optimized high EMC immunity EtherCAT slave (dual ports) with SPI-interface to the application processor. The hardware design is capable of supporting multi-protocol industrial ethernet and field-busses using the AMIC110 industrial communications processor. (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01572 — 數位輸入、D 類、IV 感測音訊放大器的立體聲評估模組參考設計

This reference design provides a high-performance stereo audio subsystem for use in PC applications. It operates off a single supply, ranging from 4.5 V to 16 V, and features the TAS2770, a digital-input Class-D audio amplifier that provides excellent noise and distortion performance and is (...)
Design guide: PDF
電路圖: PDF
封裝 引腳 下載
DSBGA (YZP) 8 檢視選項
SSOP (DCT) 8 檢視選項
VSSOP (DCU) 8 檢視選項

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