TAD5112
- DAC performance:
- DAC to Line Out Dynamic Range: 106 dB
- DAC to HP Out Dynamic Range: 102 dB
- THD+N: –95 dB
- Head Phone/Line Out output voltage:
- Differential, 2-VRMS full-scale
- Single-ended, 1-VRMS full-scale
- DAC sample Rates (fs) = 8KHz to 768KHz
- Analog Input to Output By-pass
- Battery Protection
- Signal Distortion Limiter
- Thermal Foldback
- Low Latency Filter Selection
- Programmable HPF and Biquad Filters
- I2C & SPI Control Interface
- Audio Serial Interface
- Format: TDM, I2S or Left Justified
- Word Length: 16,20,24 or 32 Bits
- Programmable PLL for Flexible Clocking
- Low Power Modes
- TBD mW for Playback
- Single Supply Operation: 1.8V or 3.3V
- I/O Supply Operation: 1.2V or 1.8V or 3.3V
The TAD5112 is a Stereo 2VRMS DAC. The TAD5112 supports both differential and Single Ended input and output. DAC Output can be configured for either Line Out or Head Phone Load. TAD5112 can drive upto TBD mW into a Headphone Load. The TAD5112 integrates programable channel gain, digital volume control, a low-jitter phase-locked loop (PLL), a programmable high-pass filter (HPF), programmable EQ and biquad filters, low-latency filter modes, and allows for sample rates up to 768 kHz. The TAD5112 supports Analog Input to Output Bypass option. Data from Analog-In and Digital-In can be mixed inside the device as well. The TAD5112 supports time-division multiplexing (TDM), I2S, or left-justified (LJ) audio formats, and can be controlled with I2C or SPI. These integrated high-performance features, along with a single supply operation, make TAD5112 an excellent choice for space-constrained audio applications.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | TAD5112 stereo audio DAC with 106 dB dynamic range datasheet | PDF | HTML | 2023年 12月 21日 |
Application note | Headset Detection for TAx52xx Family | PDF | HTML | 2024年 4月 11日 | |
Application note | TAx5x1x Synchronous Sample Rate Conversion | PDF | HTML | 2023年 12月 19日 | |
Application note | DAC Swings and Common Mode Settings in AC Coupled and DC Coupled DAC | PDF | HTML | 2023年 11月 10日 | |
Application note | Clocking Configuration of Device and Flexible Clocking For TAx5x1x Family | PDF | HTML | 2023年 11月 8日 | |
Application note | Clock Error Configuration, Detection, and Modes Supported in TAx5x1x Family | PDF | HTML | 2023年 11月 7日 |
設計與開發
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TAC5112EVM-K — TAC5112 立體聲轉碼器評估模組
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 引腳 | 下載 |
---|---|---|
VQFN (RGE) | 24 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。