首頁 介面 I2C & I3C ICs I2C & I3C level shifters, buffers & hubs

2 位元雙向 2.7 至 5.5V 熱插拔 400kHz I2C/SMBus 緩衝器

TCA4311 不建議用於新設計
儘管為了支援以前的設計而繼續生產此項產品,但我們並不建議用在新設計上。考量下列其中一項替代產品:
open-in-new 比較替代產品
功能相似於所比較的產品
TCA4311A 現行 2 位元雙向 2.7 至 5.5V 熱插拔 400kHz I2C/SMBus 緩衝器 The TCA4311A is a p2p replacement for the TCA4311. There are enhanced features related to the TCA4311A, making it most robust.

產品詳細資料

Frequency (max) (MHz) 0.4 Rating Catalog Operating temperature range (°C) -40 to 85
Frequency (max) (MHz) 0.4 Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6 VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • Operating Power-Supply Voltage Range of 2.7-V to 5.5-V
  • Supports Bidirectional Data Transfer of I2C Bus Signals
  • SDA and SCL Lines Are Buffered Which Increases Fanout
  • 1-V Precharge on All SDA and SCL Lines Prevents Corruption During Live Board Insertion and Removal From Backplane
  • SDA and SCL Input Lines Are Isolated From Outputs
  • Accommodates Standard Mode and Fast Mode I2C Devices
  • Applications Include Hot Board Insertion and Bus Extension
  • Low ICC Chip Disable of <1 μA
  • READY Open-Drain Output
  • Supports Clock Stretching, Arbitration, and Synchronization
  • Powered-Off High-Impedance I2C Pins
  • Open-Drain I2C Pins
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

  • Operating Power-Supply Voltage Range of 2.7-V to 5.5-V
  • Supports Bidirectional Data Transfer of I2C Bus Signals
  • SDA and SCL Lines Are Buffered Which Increases Fanout
  • 1-V Precharge on All SDA and SCL Lines Prevents Corruption During Live Board Insertion and Removal From Backplane
  • SDA and SCL Input Lines Are Isolated From Outputs
  • Accommodates Standard Mode and Fast Mode I2C Devices
  • Applications Include Hot Board Insertion and Bus Extension
  • Low ICC Chip Disable of <1 μA
  • READY Open-Drain Output
  • Supports Clock Stretching, Arbitration, and Synchronization
  • Powered-Off High-Impedance I2C Pins
  • Open-Drain I2C Pins
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

The TCA4311 is a hot swappable I2C bus buffer that supports I/O card insertion into a live backplane without corruption of the data and clock busses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, this device provides bidirectional buffering, keeping the backplane and card capacitances isolated. During insertion, the SDA and SCL lines are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip.

When the I2C bus is idle, the TCA4311 can be put into shutdown mode by setting the EN pin low. When EN is high, the TCA4311 resumes normal operation. It also includes an open drain READY output pin, which indicates that the backplane and card sides are connected together. When READY is high, the SDAIN and SCLIN are connected to SDAOUT and SCLOUT. When the two sides are disconnected, READY is low.

Both the backplane and card may be powered with supply voltages ranging from 2.7 V to 5.5 V, with no restrictions on which supply voltage is higher.

The TCA4311 has standard open-drain I/Os. The size of the pullup resistors to the I/Os depends on the system, but each side of this buffer must have a pullup resistor. The device is designed to work with Standard Mode and Fast Mode I2C devices in addition to SMBus devices. Standard Mode I2C devices only specify 3 mA in a generic I2C system where Standard Mode devices and multiple masters are possible. Under certain conditions, high termination currents can be used.

The TCA4311 is a hot swappable I2C bus buffer that supports I/O card insertion into a live backplane without corruption of the data and clock busses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, this device provides bidirectional buffering, keeping the backplane and card capacitances isolated. During insertion, the SDA and SCL lines are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip.

When the I2C bus is idle, the TCA4311 can be put into shutdown mode by setting the EN pin low. When EN is high, the TCA4311 resumes normal operation. It also includes an open drain READY output pin, which indicates that the backplane and card sides are connected together. When READY is high, the SDAIN and SCLIN are connected to SDAOUT and SCLOUT. When the two sides are disconnected, READY is low.

Both the backplane and card may be powered with supply voltages ranging from 2.7 V to 5.5 V, with no restrictions on which supply voltage is higher.

The TCA4311 has standard open-drain I/Os. The size of the pullup resistors to the I/Os depends on the system, but each side of this buffer must have a pullup resistor. The device is designed to work with Standard Mode and Fast Mode I2C devices in addition to SMBus devices. Standard Mode I2C devices only specify 3 mA in a generic I2C system where Standard Mode devices and multiple masters are possible. Under certain conditions, high termination currents can be used.

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類型 標題 日期
* Data sheet TCA4311 Hot Swappable 2-Wire Bus Buffers datasheet (Rev. A) 2014年 6月 12日

設計與開發

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模擬型號

HSPICE Model for TCA4311

SCPJ002.ZIP (237 KB) - HSpice Model
模擬型號

TCA4311 IBIS Model

SCPM012.ZIP (44 KB) - IBIS Model
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具

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TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
封裝 引腳 下載
SOIC (D) 8 檢視選項
VSSOP (DGK) 8 檢視選項

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 資格摘要
  • 進行中可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

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