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隔離式閘極驅動器

UCC21225A

現行

採用雙輸入、5V UVLO 和 LGA 封裝的 2.5kVrms、4A/6A 雙通道絕緣式閘極驅動器

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產品規格表

UCC21225A

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 2 Isolation rating Functional Withstand isolation voltage (VISO) (Vrms) 2500 Working isolation voltage (VIOWM) (Vrms) 792 Transient isolation voltage (VIOTM) (VPK) 3535 Power switch GaNFET, IGBT, MOSFET, SiCFET Peak output current (A) 6 Features Disable, Programmable dead time Output VCC/VDD (max) (V) 25 Output VCC/VDD (min) (V) 6.5 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 18 Propagation delay time (µs) 0.019 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Bootstrap supply voltage (max) (V) 792 Rise time (ns) 6 Fall time (ns) 7 Undervoltage lockout (typ) (V) 5
Number of channels 2 Isolation rating Functional Withstand isolation voltage (VISO) (Vrms) 2500 Working isolation voltage (VIOWM) (Vrms) 792 Transient isolation voltage (VIOTM) (VPK) 3535 Power switch GaNFET, IGBT, MOSFET, SiCFET Peak output current (A) 6 Features Disable, Programmable dead time Output VCC/VDD (max) (V) 25 Output VCC/VDD (min) (V) 6.5 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 18 Propagation delay time (µs) 0.019 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Bootstrap supply voltage (max) (V) 792 Rise time (ns) 6 Fall time (ns) 7 Undervoltage lockout (typ) (V) 5
VLGA (NPL) 13 25 mm² 5 x 5
  • Universal: Dual Low-Side, Dual High-Side or Half-Bridge Driver
  • 5 x 5 mm, Space-Saving LGA-13 Package
  • Switching Parameters:
    • 19-ns Typical Propagation Delay
    • 5-ns Maximum Delay Matching
    • 6-ns Maximum Pulse-Width Distortion
  • CMTI Greater than 100-V/ns
  • 4-A Peak Source, 6-A Peak Sink Output
  • TTL and CMOS Compatible Inputs
  • 3-V to 18-V Input VCCI Range
  • Up to 25-V VDD with 5-V UVLO
  • Programmable Overlap and Dead Time
  • Rejects Input Transients Shorter than 5-ns
  • Fast Disable for Power Sequencing
  • Safety-Related Certifications:
    • 3535-VPK Isolation per DIN V VDE V 0884-11:2017-01
    • 2500-VRMS Isolation for 1 Minute per UL 1577
    • CQC per GB4943.1-2011 (Planned)
  • Universal: Dual Low-Side, Dual High-Side or Half-Bridge Driver
  • 5 x 5 mm, Space-Saving LGA-13 Package
  • Switching Parameters:
    • 19-ns Typical Propagation Delay
    • 5-ns Maximum Delay Matching
    • 6-ns Maximum Pulse-Width Distortion
  • CMTI Greater than 100-V/ns
  • 4-A Peak Source, 6-A Peak Sink Output
  • TTL and CMOS Compatible Inputs
  • 3-V to 18-V Input VCCI Range
  • Up to 25-V VDD with 5-V UVLO
  • Programmable Overlap and Dead Time
  • Rejects Input Transients Shorter than 5-ns
  • Fast Disable for Power Sequencing
  • Safety-Related Certifications:
    • 3535-VPK Isolation per DIN V VDE V 0884-11:2017-01
    • 2500-VRMS Isolation for 1 Minute per UL 1577
    • CQC per GB4943.1-2011 (Planned)

The UCC21225A is an isolated dual-channel gate driver with 4-A source and 6-A sink peak current in a 5-mm x 5-mm LGA-13 package. It is designed to drive power transistors up to 5-MHz with best-in-class propagation delay and pulse-width distortion.

The input side is isolated from the two output drivers by a 2.5-kVRMS isolation barrier, with 100-V/ns minimum common-mode transient immunity (CMTI). Internal functional isolation between the two secondary side drivers allows working voltage up to 700-VDC.

This driver can be configured as two low-side, two high-side, or a half-bridge driver with programmable dead time (DT). A disable pin shuts down both outputs simultaneously when it is set high, and allows normal operation when left open or grounded.

The device accepts VDD supply voltages up to 25-V. A wide input VCCI range from 3-V to 18-V makes the driver suitable for interfacing with both analog and digital controllers. All the supply voltage pins have under voltage lock-out (UVLO) protection.

With all these advanced features, the UCC21225A enables high power density, high efficiency, and robustness in a wide variety of power applications.

The UCC21225A is an isolated dual-channel gate driver with 4-A source and 6-A sink peak current in a 5-mm x 5-mm LGA-13 package. It is designed to drive power transistors up to 5-MHz with best-in-class propagation delay and pulse-width distortion.

The input side is isolated from the two output drivers by a 2.5-kVRMS isolation barrier, with 100-V/ns minimum common-mode transient immunity (CMTI). Internal functional isolation between the two secondary side drivers allows working voltage up to 700-VDC.

This driver can be configured as two low-side, two high-side, or a half-bridge driver with programmable dead time (DT). A disable pin shuts down both outputs simultaneously when it is set high, and allows normal operation when left open or grounded.

The device accepts VDD supply voltages up to 25-V. A wide input VCCI range from 3-V to 18-V makes the driver suitable for interfacing with both analog and digital controllers. All the supply voltage pins have under voltage lock-out (UVLO) protection.

With all these advanced features, the UCC21225A enables high power density, high efficiency, and robustness in a wide variety of power applications.

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類型 標題 日期
* Data sheet UCC21225A 4-A, 6-A, 2.5-kVRMS Isolated Dual-Channel Gate Driver in LGA datasheet (Rev. A) PDF | HTML 2018年 2月 7日
Certificate VDE Certificate for Basic Isolation for DIN EN IEC 60747-17 (Rev. W) 2024年 1月 31日
Application brief External Gate Resistor Selection Guide (Rev. A) 2020年 2月 28日
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 2020年 2月 28日
Application brief How to Drive High Voltage GaN FETs with UCC21220A 2019年 3月 6日
Certificate UL Certification E181974 Vol 4. Sec 8 (Rev. A) 2018年 7月 23日
Certificate CQC Product Certificate 2 2018年 2月 7日
EVM User's guide Using the UCC21225AEVM-365 2017年 3月 14日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

UCC21225AEVM-365 — UCC21225A 4A、6A 5.7kVRMS 隔離式雙通道閘極驅動器評估模組

UCC21225AEVM-365 is designed for evaluating UCC21225ANPL, which is an isolated dual-channel gate driver with 4-A source and 6-A sink peak current capability in a 5x5 LGA package. This EVM can be used as a reference design for driving power MOSFETs, IGBTs, and SiC MOSFETs with UCC21225A pin (...)
使用指南: PDF
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模擬型號

UCC21225A PSpice Transient Model

SLUM574.ZIP (55 KB) - PSpice Model
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模擬型號

UCC21225A Unencrypted PSpice Transient Model

SLUM575.ZIP (4 KB) - PSpice Model
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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參考設計

PMP40988 — 可變頻率、ZVS、5-kW、GaN 架構、二相圖騰柱 PFC 參考設計

此參考設計為高密度且高效率的 5-kW 圖騰柱功率因數校正 (PFC) 設計。此設計採用具可變頻率和零電壓切換 (ZVS) 的雙相圖騰柱 PFC 運作。此控件採用新拓撲與改良三角電流模式 (iTCM) 實現小尺寸與高效率。該設計在 TMS320F280049C 微控制器內部使用高性能處理核心，以在廣泛的操作範圍內保持高效率。PFC 採用介於 100 kHz 和 800 kHz 之間的可變頻率來運作。開放訊框功率密度 120 W/in3 實現 99% 的峰值系統效率。
Test report: PDF
參考設計

PMP23332 — 交錯式和多相反相降壓-升壓轉換器參考設計

此參考設計運用 UCD3138064A 做為數位控制器，使用支援雙相峰值電流模式控制的能力來控制反相降壓升壓。此設計採用軟切換技術提升電源效率。輸入電壓範圍為 -62 V 至 -36 V。輸出電壓範圍可在 28 V 至 52 V 之間調整。預設輸出電壓為 48-V，最大電流為 14 A。
Test report: PDF
參考設計

PMP20587 — 反向降壓升壓參考設計

This reference design uses UCD3138064A as a digital controller to control two-phase two-rail inverting buck-boost. This non-isolated converter is used for wireless radio power. The input voltage is from -35 V to -60 V. There are two outputs. The default output voltage of rail 1 is 32 V and max (...)
Test report: PDF
電路圖: PDF
參考設計

PMP21943 — 適用於功率放大器的 48-V/25-A 負到正同步降壓-升壓參考設計

This reference design is a negative-to-positive synchronous buck-boost converter for power amplifier applications. The circuit is powered from the nominal -48-V system source to provide an output voltage of +48 V at 25 A. The design uses two dual synchronous boost controllers for 4-phase operation (...)
Test report: PDF
電路圖: PDF
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