UCC21551-Q1
- Universal: dual low-side, dual high-side or half-bridge driver
- AEC-Q100 qualified with the following result
- Device temperature grade 1
- Junction temperature range –40 to +150°C
- Up to 4A peak source and 6A peak sink output
- Common-mode transient immunity (CMTI) greater than 125V/ns
- Up to 25V VDD output drive supply
- 5V,8V, 12V and 17V VDD UVLO options
- Switching parameters:
- 33ns typical propagation delay
- 5ns maximum delay matching
- 6ns maximum pulse-width distortion
- 10µs maximum VDD power-up delay
- UVLO protection for all power supplies
- Fast enable for power sequencing
The UCC21551x-Q1 is an isolated dual channel gate driver family with programmable dead time and wide temperature range. It is designed with 4A peak-source and 6A peak-sink current to drive power MOSFET, SiC, and IGBT transistors.
The UCC21551x-Q1 can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. The input side is isolated from the two output drivers by a 5kVRMS isolation barrier, with a minimum of 125V/ns common-mode transient immunity (CMTI).
Protection features include: resistor programmable dead time, disable feature to shut down both outputs simultaneously, and integrated de-glitch filter that rejects input transients shorter than 5ns. All supplies have UVLO protection.
With all these advanced features, the UCC21551x-Q1 device enables high efficiency, high power density, and robustness in a wide variety of power applications.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | UCC21551x-Q1 Automotive 4A, 6A, Reinforced Isolation Dual-Channel Gate Driver datasheet (Rev. F) | PDF | HTML | 2024年 5月 8日 |
Functional safety information | UCC21551x-Q1 Functional Safety FIT Rate, FMD and Pin FMA | PDF | HTML | 2023年 9月 13日 |
設計與開發
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UCC21551CQEVM-079 — 適用於 4-A、6-A 雙通道隔離式閘極驅動器的 UCC21551 評估模組
UCC21551CQEVM 是包含多個測試點和跳線的雙層銅纜電路板,以全面評估 UCC21551 裝置功能。該 EVM 具有 PWM 輸入控制、板載可調電源、用於離散 FET 的插座、用於低壓側保護的外部主動箝位、靴帶式高壓側、負閘極電壓功能、可配置失效時間開關、EN/DIS 跳線、適用於 Wolfspeed XM3 SiC 式半橋電源模組的插座。此配置經過最佳化,可將各通道的迴圈區域降至最低,並可放置旁路電容,以最小的雜訊干擾提供清晰銳利的訊號讀數。
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 引腳 | 下載 |
---|---|---|
SOIC (DWK) | 14 | 檢視選項 |
訂購與品質
- RoHS
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- MTBF/FIT 估算值
- 材料內容
- 資格摘要
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