Simple Open Real-Time Ethernet (SORTE) Master With PRU-ICSS Reference Design
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Key Document


The TIDEP-0085 reference design implements a Simple Open Real-Time Ethernet (SORTE) master with the Programmable Real-time Unit and Industrial Communication Subsystem (PRU-ICSS). SORTE enables customer applications to exchange process data between the master and devices in a 4 µs cycle time. The design contains open source PRU firmware to enable customer to differentiate their products.

The SORTE protocol includes device discovery, parametrization, PHY and cable delay measurement, synchronization and process data exchange.

  • SORTE master reference implementation
  • Enables 4 µs cycle time to exchange process data
  • PRU firmware provided in source code
  • Fully customizable PRU firmware

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AM3359 Industrial Communications Engine (ICE)


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TI Devices (3)

Order samples, get tools and find more information on the TI products in this reference design.

Part Number Name Product Family Sample & Buy Design Kits & Evaluation Modules
AM3357  Sitara processor: Arm Cortex-A8, EtherCAT, PRU-ICSS, CAN  Sitara processors  Sample & Buy View Design Kits & Evaluation Modules
DP83822I  Low-power, robust 10/100-Mbps Ethernet PHY transceiver with 16-kV ESD  Ethernet  Sample & Buy View Design Kits & Evaluation Modules
TLK110  Industrial 10/100 Ethernet PHY  Ethernet  Sample & Buy View Design Kits & Evaluation Modules

CAD/CAE symbols

Part # Package | Pins CAD File (.bxl) STEP Model (.stp)
AM3357 Download Download
DP83822I Download
TLK110 Download Download

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Technical Documents

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Datasheet (1)
Title Type Size (KB) Date
PDF 3216 06 Aug 2018
User guides (1)
Title Type Size (KB) Date
PDF 2694 01 May 2017
Design files (5)
Title Type Size (KB) Date
ZIP 3012 01 May 2017
ZIP 765 01 May 2017
ZIP 206 01 May 2017
PDF 104 01 May 2017
PDF 398 01 May 2017
Related Tools & Software

Reference Designs  ( 3 )

Design Kits & Evaluation Modules  ( 1 )

Name Part Number Tool Type
AM3359 Industrial Communications Engine  TMDSICE3359  Development Kits 

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