Parallel Camera Interface for Sitara Processors
TIDEP0018
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Description

This camera interface design connects to a 10-bit parallel interface to the AM335x general purpose memory controller (GPMC) 16-bit multiplexed address/data bus. This design consumes roughly 150mW less power than typical USB solutions, and is ideal for applications like portable data terminals, ruggedized handhelds, portable consumer, industrial handhelds and others. The reference design is based on the QuickLogic 3.1 MP Camera Sensor (using an Aptina 3.1 MP sensor) connected to a camera expansion board. Together, they connect to the BeagleBone platform. The BeagleBone and the QuickLogic 3.1 MP camera add-on board are available for purchase.

More information on QuickLogic: http://www.quicklogic.com
More information about BeagleBone: http://www.ti.com/tool/beaglebn

More information about the QuickLogic 3.1 MP camera add-on board for the BeagleBone, including design files and software: http://www.quicklogic.com/solutions/reference-designs/ti-sitara-beaglebone-camera-cape/

Features
  • Supports up to 5MP camera at 10fps with DMA
  • Up to 30 frames per second (fps) at VGA (640 x 480) resolution
  • Reduces system power consumption up to 150mW
  • No software effort required for OEM
  • 6x6mm, non-HDI rules package
  • This is an example sub-system design that includes schematics, BOM, Gerbers and other design files.

See the Important Notice and Disclaimer covering reference designs and other TI resources.


  



Schematic/Block Diagram

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Part Number Status

TIDEP0018:
Parallel Camera interface for Sitara Processors

ACTIVE

TI Devices (5)

Order samples, get tools and find more information on the TI products in this reference design.

Part Number Name Product Family Sample & Buy Design Kits & Evaluation Modules
AM3358  Sitara processor: Arm Cortex-A8, 3D graphics, PRU-ICSS, CAN  Sitara processors  Sample & Buy View Design Kits & Evaluation Modules
SN74AVC1T45  Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage-Level Shifting and 3-State Outputs  Voltage level translation  Sample & Buy View Design Kits & Evaluation Modules
SN74LVC1G07  Single Buffer/Driver With Open-Drain Output  Buffer/driver  Sample & Buy View Design Kits & Evaluation Modules
TPS737  Single Output LDO, 1A, Adj. (1.2 to 5.0V), Reverse Current Protection  Power management  Sample & Buy View Design Kits & Evaluation Modules
TXS0102  2-Bit Bidirectional Voltage-Level Shifter for Open-Drain and Push-Pull Application  Voltage level translation  Sample & Buy View Design Kits & Evaluation Modules

CAD/CAE symbols

Part # Package | Pins CAD File (.bxl) STEP Model (.stp)
AM3358 NFBGA (ZCE)| 298 Download
Download Download
SN74AVC1T45 Download Download
Download Download
Download Download
Download -
Download -
SN74LVC1G07 Download -
Download Download
Download Download
Download
Download Download
Download -
Download Download
Download Download
TPS737 Download Download
Download Download
Download Download
TXS0102 Download Download
Download Download
Download
Download Download
Download -
Download -

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Step 2: Download the Symbol and Footprint from the CAD.bxl file table.


Technical Documents

See the Important Notice and Disclaimer covering reference designs and other TI resources.

Third party documents (2)
Title Date Type
BeagleBone 3.1MP Camera Cape System Reference Manual 30 Jul 2014
Low Power Camera Interface to BeagleBone Reference Design [QuickLogic Information Page] 30 Jul 2014
User guides (1)
Title Type Size (KB) Date
PDF 82 29 Jul 2014
Design files (5)
Title Type Size (KB) Date
ZIP 141 30 Jul 2014
ZIP 1460 30 Jul 2014
ZIP 1460 30 Jul 2014
ZIP 22 30 Jul 2014
ZIP 150 30 Jul 2014

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