Parallel Camera Interface for Sitara Processors

(ACTIVE) TIDEP0018

Description & Features

Technical Documents

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Description

This camera interface design connects to a 10-bit parallel interface to the AM335x general purpose memory controller (GPMC) 16-bit multiplexed address/data bus. This design consumes roughly 150mW less power than typical USB solutions, and is ideal for applications like portable data terminals, ruggedized handhelds, portable consumer, industrial handhelds and others. The reference design is based on the QuickLogic 3.1 MP Camera Sensor (using an Aptina 3.1 MP sensor) connected to a camera expansion board. Together, they connect to the BeagleBone platform. The BeagleBone and the QuickLogic 3.1 MP camera add-on board are available for purchase.

More information on QuickLogic: http://www.quicklogic.com
More information about BeagleBone: http://www.ti.com/tool/beaglebn

More information about the QuickLogic 3.1 MP camera add-on board for the BeagleBone, including design files and software: http://www.quicklogic.com/solutions/reference-designs/ti-sitara-beaglebone-camera-cape/

Features
  • Supports up to 5MP camera at 10fps with DMA
  • Up to 30 frames per second (fps) at VGA (640 x 480) resolution
  • Reduces system power consumption up to 150mW
  • No software effort required for OEM
  • 6x6mm, non-HDI rules package
  • This is an example sub-system design that includes schematics, BOM, Gerbers and other design files.

View the Important Notice for TI Designs covering authorized use, intellectual property matters and disclaimers.


  




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Part Number Status

TIDEP0018:
Parallel Camera interface for Sitara Processors

ACTIVE

TI Devices (5)

Order samples, get tools and find more information on the TI products in this reference design.

Part Number Name Product Family Sample & Buy Design Kits & Evaluation Modules
AM3358  Sitara Processor: ARM Cortex-A8, 3D Graphics, PRU-ICSS  Arm Cortex-A8  Sample & Buy View Design Kits & Evaluation Modules
SN74AVC1T45  Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage-Level Shifting and 3-State Outputs  Voltage Level Translation  Sample & Buy View Design Kits & Evaluation Modules
SN74LVC1G07  Single Buffer/Driver With Open-Drain Output  Buffer/Driver  Sample & Buy View Design Kits & Evaluation Modules
TPS737  Single Output LDO, 1A, Adj. (1.2 to 5.0V), Reverse Current Protection  Linear Regulator (LDO)  Sample & Buy View Design Kits & Evaluation Modules
TXS0102  2-Bit Bidirectional Voltage-Level Shifter for Open-Drain and Push-Pull Application  Voltage Level Translation  Sample & Buy View Design Kits & Evaluation Modules

Technical Documents

View the Important Notice for TI Designs covering authorized use, intellectual property matters and disclaimers.

Third party documents (2)
Title Date Type
BeagleBone 3.1MP Camera Cape System Reference Manual 30 Jul 2014
Low Power Camera Interface to BeagleBone Reference Design [QuickLogic Information Page] 30 Jul 2014
User guides (1)
Title Abstract Type Size (KB) Date Views
PDF 82 29 Jul 2014 186
Design files (5)
Title Abstract Type Size (KB) Date Views
ZIP 141 30 Jul 2014 23
ZIP 1460 30 Jul 2014 130
ZIP 1460 30 Jul 2014 53
ZIP 22 30 Jul 2014 21
ZIP 150 30 Jul 2014 250

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