SNAS480N May   2010  – August 2015 ADC12D1000 , ADC12D1600

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Static Converter
    6. 6.6  Electrical Characteristics: Dynamic Converter
    7. 6.7  Electrical Characteristics: Analog Input/Output and Reference
    8. 6.8  Electrical Characteristics: I-Channel To Q-Channel
    9. 6.9  Electrical Characteristics: Converter and Sampling Clock
    10. 6.10 Electrical Characteristics: Autosync Feature
    11. 6.11 Electrical Characteristics: Digital Control and Output Pin
    12. 6.12 Electrical Characteristics: Power Supply
    13. 6.13 Electrical Characteristics: AC
    14. 6.14 Timing Requirements: Serial Port Interface
    15. 6.15 Timing Requirements: Calibration
    16. 6.16 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Control and Adjust
        1. 7.3.1.1 AC-DC-Coupled Mode
        2. 7.3.1.2 Input Full-Scale Range Adjust
        3. 7.3.1.3 Input Offset Adjust
        4. 7.3.1.4 DES Timing Adjust
        5. 7.3.1.5 Sampling Clock Phase Adjust
      2. 7.3.2 Output Control and Adjust
        1. 7.3.2.1 DDR Clock Phase
        2. 7.3.2.2 LVDS Output Differential Voltage
        3. 7.3.2.3 LVDS Output Common-Mode Voltage
        4. 7.3.2.4 Output Formatting
        5. 7.3.2.5 Test Pattern Mode
        6. 7.3.2.6 Time Stamp
      3. 7.3.3 Calibration Feature
        1. 7.3.3.1 Calibration Control Pins and Bits
        2. 7.3.3.2 How to Execute a Calibration
        3. 7.3.3.3 Power-On Calibration
        4. 7.3.3.4 On-Command Calibration
        5. 7.3.3.5 Calibration Adjust
        6. 7.3.3.6 Read/Write Calibration Settings
        7. 7.3.3.7 Calibration and Power-Down
        8. 7.3.3.8 Calibration and the Digital Outputs
      4. 7.3.4 Power Down
    4. 7.4 Device Functional Modes
      1. 7.4.1 DES/Non-DES Mode
      2. 7.4.2 Demux/Non-Demux Mode
    5. 7.5 Programming
      1. 7.5.1 Control Modes
        1. 7.5.1.1 Non-Extended Control Mode
          1. 7.5.1.1.1  Dual Edge Sampling Pin (DES)
          2. 7.5.1.1.2  Non-Demultiplexed Mode Pin (NDM)
          3. 7.5.1.1.3  Dual Data Rate Phase Pin (DDRPH)
          4. 7.5.1.1.4  Calibration Pin (CAL)
          5. 7.5.1.1.5  Calibration Delay Pin (CALDLY)
          6. 7.5.1.1.6  Power-Down I-Channel Pin (PDI)
          7. 7.5.1.1.7  Power-Down Q-Channel Pin (PDQ)
          8. 7.5.1.1.8  Test Pattern Mode Pin (TPM)
          9. 7.5.1.1.9  Full-Scale Input Range Pin (FSR)
          10. 7.5.1.1.10 AC-DC-Coupled Mode Pin (VCMO)
          11. 7.5.1.1.11 LVDS Output Common-Mode Pin (VBG)
        2. 7.5.1.2 Extended Control Mode
          1. 7.5.1.2.1 The Serial Interface
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 The Analog Inputs
        1. 8.1.1.1 Acquiring the Input
        2. 8.1.1.2 Driving the ADC in DES Mode
        3. 8.1.1.3 FSR and the Reference Voltage
        4. 8.1.1.4 Out-of-Range Indication
        5. 8.1.1.5 Maximum Input Range
        6. 8.1.1.6 AC-Coupled Input Signals
        7. 8.1.1.7 DC-Coupled Input Signals
        8. 8.1.1.8 Single-Ended Input Signals
      2. 8.1.2 The Clock Inputs
        1. 8.1.2.1 CLK Coupling
        2. 8.1.2.2 CLK Frequency
        3. 8.1.2.3 CLK Level
        4. 8.1.2.4 CLK Duty Cycle
        5. 8.1.2.5 CLK Jitter
        6. 8.1.2.6 CLK Layout
      3. 8.1.3 The LVDS Outputs
        1. 8.1.3.1 Common-Mode and Differential Voltage
        2. 8.1.3.2 Output Data Rate
        3. 8.1.3.3 Terminating Unused LVDS Output Pins
      4. 8.1.4 Synchronizing Multiple ADC12D1x00s in a System
        1. 8.1.4.1 Autosync Feature
        2. 8.1.4.2 DCLK Reset Feature
      5. 8.1.5 Recommended System Chips
        1. 8.1.5.1 Temperature Sensor
        2. 8.1.5.2 Clocking Device
        3. 8.1.5.3 Amplifiers for the Analog Input
        4. 8.1.5.4 Balun Recommendations for Analog Input
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 System Power-On Considerations
      1. 9.1.1 Power-On, Configuration, and Calibration
      2. 9.1.2 Power-On and Data Clock (Dclk)
    2. 9.2 Supply Voltage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Planes
      2. 10.1.2 Bypass Capacitors
      3. 10.1.3 Ground Planes
      4. 10.1.4 Power System Example
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Specification Definitions
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

11.1.1.1 Specification Definitions

    APERTURE (SAMPLING) DELAYis the amount of delay, measured from the sampling edge of the CLK input, after which the signal present at the input pin is sampled inside the device.
    APERTURE JITTER (tAJ)is the variation in aperture delay from sample-to-sample. Aperture jitter can be effectively considered as noise at the input.
    CODE ERROR RATE (CER)is the probability of error and is defined as the probable number of word errors on the ADC output per unit of time divided by the number of words seen in that amount of time. A CER of 10-18 corresponds to a statistical error in one word about every 31.7 years for the ADC12D1000.
    CLOCK DUTY CYCLEis the ratio of the time that the clock waveform is at a logic high to the total time of one clock period.
    DIFFERENTIAL NON-LINEARITY (DNL)is the measure of the maximum deviation from the ideal step size of 1 LSB. It is measured at the relevant sample rate, fCLK, with fIN = 1MHz sine wave.
    EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS)is another method of specifying Signal-to-Noise and Distortion Ratio, or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and states that the converter is equivalent to a perfect ADC of this many (ENOB) number of bits.
    FULL POWER BANDWIDTH (FPBW)is a measure of the frequency at which the reconstructed output fundamental drops to 3 dB below its low frequency value for a full-scale input.
    GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Offset and Full-Scale Errors. The Positive Gain Error is the Offset Error minus the Positive Full-Scale Error. The Negative Gain Error is the Negative Full-Scale Error minus the Offset Error. The Gain Error is the Negative Full-Scale Error minus the Positive Full-Scale Error; it is also equal to the Positive Gain Error plus the Negative Gain Error.
    INTEGRAL NON-LINEARITY (INL)is a measure of worst case deviation of the ADC transfer function from an ideal straight line drawn through the ADC transfer function. The deviation of any given code from this straight line is measured from the center of that code value step. The best fit method is used.
    INTERMODULATION DISTORTION (IMD) is a measure of the near-in 3rd order distortion products (2f2 - f1, 2f1 - f2) which occur when two tones which are close in frequency (f1, f2) are applied to the ADC input. It is measured from the input tones level to the higher of the two distortion products (dBc) or simply the level of the higher of the two distortion products (dBFS). The input tones are typically -7dBFS.
    LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is
    Equation 4. VFS / 2N

    where

    • VFS is the differential full-scale amplitude VIN_FSR as set by the FSR input and "N" is the ADC resolution in bits, which is 10 for the ADC12D1x00.
    LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS) DIFFERENTIAL OUTPUT VOLTAGE (VID and VOD) is two times the absolute value of the difference between the VD+ and VD- signals; each signal measured with respect to Ground. VOD peak is VOD,P= (VD+ - VD-) and VOD peak-to-peak is VOD,P-P= 2*(VD+ - VD-); for this product, the VOD is measured peak-to-peak.
    ADC12D1000 ADC12D1600 30091646.gifFigure 84. LVDS Output Signal Levels
    LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpoint between the D+ and D- pins output voltage with respect to ground; that is, [(VD+) +( VD-)]/2. See Figure 84.
    MISSING CODESare those output codes that are skipped and will never appear at the ADC outputs. These codes cannot be reached with any input value.
    MSB (MOST SIGNIFICANT BIT)is the bit that has the largest value or weight. Its value is one half of full scale.
    NEGATIVE FULL-SCALE ERROR (NFSE)is a measure of how far the first code transition is from the ideal 1/2 LSB above a differential −VIN/2 with the FSR pin low. For the ADC12D1x00 the reference voltage is assumed to be ideal, so this error is a combination of full-scale error and reference voltage error.
    NOISE FLOOR DENSITYis a measure of the power density of the noise floor, expressed in dBFS/Hz and dBm/Hz. '0 dBFS' is defined as the power of a sinusoid which precisely uses the full-scale range of the ADC.
    NOISE POWER RATIO (NPR) is the ratio of the sum of the power outside the notched bins to the sum of the power in an equal number of bins inside the notch, expressed in dB.
    OFFSET ERROR (VOFF)is a measure of how far the mid-scale point is from the ideal zero voltage differential input. Offset Error = Actual Input causing average of 8-k samples to result in an average code of 2047.5.
    OUTPUT DELAY (tOD)is the time delay (in addition to Latency) after the rising edge of CLK+ before the data update is present at the output pins.
    OVER-RANGE RECOVERY TIMEis the time required after the differential input voltages goes from ±1.2 V to 0 V for the converter to recover and make a conversion with its rated accuracy.
    PIPELINE DELAY (LATENCY)is the number of input clock cycles between initiation of conversion and when that data is presented to the output driver stage. The data lags the conversion by the Latency plus the tOD.
    POSITIVE FULL-SCALE ERROR (PFSE)is a measure of how far the last code transition is from the ideal 1-1/2 LSB below a differential +VIN/2. For the ADC12D1x00 the reference voltage is assumed to be ideal, so this error is a combination of full-scale error and reference voltage error.
    SIGNAL TO NOISE RATIO (SNR)is the ratio, expressed in dB, of the rms value of the fundamental for a single-tone to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC.
    SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD)is the ratio, expressed in dB, of the rms value of the fundamental for a single-tone to the rms value of all of the other spectral components below half the input clock frequency, including harmonics but excluding DC.
    SPURIOUS-FREE DYNAMIC RANGE (SFDR)is the difference, expressed in dB, between the rms values of the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input, excluding DC.
    θJAis the thermal resistance between the junction to ambient.
    θJC1represents the thermal resistance between the die and the exposed metal area on the top of the HSBGA package.
    θJC2represents the thermal resistance between the die and the center group of balls on the bottom of the HSBGA package.
    TOTAL HARMONIC DISTORTION (THD)is the ratio expressed in dB, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as
    Equation 5. ADC12D1000 ADC12D1600 30091605.gif

    where

    • Af1 is the RMS power of the fundamental (output) frequency and Af2 through Af10 are the RMS power of the first 9 harmonic frequencies in the output spectrum.
    Second Harmonic Distortion (2nd Harm)is the difference, expressed in dB, between the RMS power in the input frequency seen at the output and the power in its 2nd harmonic level at the output.
    Third Harmonic Distortion (3rd Harm)is the difference expressed in dB between the RMS power in the input frequency seen at the output and the power in its 3rd harmonic level at the output.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation, see the following:

  • AN-1126 BGA (Ball Grid Array), SNOA021
  • AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature, SNAA073

11.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

Table 35. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY
ADC12D1000 Click here Click here Click here Click here Click here
ADC12D1600 Click here Click here Click here Click here Click here

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.