Product details

Sample rate (Max) (MSPS) 1000, 2000 Resolution (Bits) 12 Number of input channels 2, 1 Interface type Parallel LVDS Analog input BW (MHz) 2800 Features Ultra High Speed Rating Catalog Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 3380 Architecture Folding Interpolating SNR (dB) 60.2 ENOB (Bits) 9.6 SFDR (dB) 71 Operating temperature range (C) -40 to 85 Input buffer Yes
Sample rate (Max) (MSPS) 1000, 2000 Resolution (Bits) 12 Number of input channels 2, 1 Interface type Parallel LVDS Analog input BW (MHz) 2800 Features Ultra High Speed Rating Catalog Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 3380 Architecture Folding Interpolating SNR (dB) 60.2 ENOB (Bits) 9.6 SFDR (dB) 71 Operating temperature range (C) -40 to 85 Input buffer Yes
BGA (NXA) 292 729 mm² 27 x 27
  • Configurable to Either 2.0/3.2 GSPS Interleaved
    or 1.0/1.6 GSPS Dual ADC
  • Pin-Compatible With ADC10D1x00 and
    ADC12D1x00
  • Internally Terminated, Buffered, Differential
    Analog Inputs
  • Interleaved Timing Automatic and Manual Skew
    Adjust
  • Test Patterns at Output for System Debug
  • Programmable 15-bit Gain and 12-bit Plus Sign
    Offset
  • Programmable tAD Adjust Feature
  • 1:1 Non-demuxed or 1:2 Demuxed LVDS Outputs
  • AutoSync Feature for Multi-Chip Systems
  • Single 1.9-V ± 0.1-V Power Supply
  • Configurable to Either 2.0/3.2 GSPS Interleaved
    or 1.0/1.6 GSPS Dual ADC
  • Pin-Compatible With ADC10D1x00 and
    ADC12D1x00
  • Internally Terminated, Buffered, Differential
    Analog Inputs
  • Interleaved Timing Automatic and Manual Skew
    Adjust
  • Test Patterns at Output for System Debug
  • Programmable 15-bit Gain and 12-bit Plus Sign
    Offset
  • Programmable tAD Adjust Feature
  • 1:1 Non-demuxed or 1:2 Demuxed LVDS Outputs
  • AutoSync Feature for Multi-Chip Systems
  • Single 1.9-V ± 0.1-V Power Supply

The 12-bit, 2.0/3.2 GSPS ADC12D1x00 device is the latest advance in TI’s Ultra High-Speed ADC family and builds upon the features, architecture, and functionality of the 10-bit GHz family of ADCs.

The ADC12D1x00 provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and support programmable common-mode voltage.

The ADC12D1x00 is packaged in a leaded or lead-free 292-pin thermally enhanced BGA package over the rated industrial temperature range of –40°C to 85°C.

The 12-bit, 2.0/3.2 GSPS ADC12D1x00 device is the latest advance in TI’s Ultra High-Speed ADC family and builds upon the features, architecture, and functionality of the 10-bit GHz family of ADCs.

The ADC12D1x00 provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and support programmable common-mode voltage.

The ADC12D1x00 is packaged in a leaded or lead-free 292-pin thermally enhanced BGA package over the rated industrial temperature range of –40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet ADC12D1x00 12-Bit, 2.0/3.2 GSPS Ultra High-Speed ADC datasheet (Rev. N) 31 Aug 2015
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
Technical article How to achieve fast frequency hopping 03 Mar 2019
Technical article RF sampling: Learning more about latency 09 Feb 2017
Application note AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) 03 Feb 2017
Technical article Why phase noise matters in RF sampling converters 28 Nov 2016
Application note Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigat 09 Dec 2013
Application note AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C) 01 May 2013
User guide Schematic and Layout Recommendations for the GSPS ADC 29 Apr 2013
Application note AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) 26 Apr 2013
Application note From Sample Instant to Data Output: Understanding Latency in the GSPS ADC 18 Dec 2012
More literature ADC12D1x00 12-bit ADC Family: Ultra High-Speed 12-bit ADCs up to 3.6 GSPS 16 May 2012
User guide 12-Bit, Dual 1.6/1.8 GSPS or Single 3.2/3.6 GSPS Ref Bd User Guide 25 Jan 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC12D1600RB — 12-bit, dual 1.6-/1.8-GSPS or single 3.2-/3.6-GSPS ADC reference board

The ADC12D1600 is the latest advance in TI's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 12-bit resolution for dual channels at sampling rates of up to 1.0/1.6/1.8 GSPS (Non-Interleave Mode) or for a single channel up to (...)

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Application software & framework

WAVEVISION5 — Data acquisition and analysis software

WaveVision 5 software is part of the WaveVision evaluation system that also includes WaveVision 5 Data Capture Board. The WaveVision 5 system is an easy-to-use data acquisition and analysis tool, designed to help users evaluate Texas Instruments' Signal Path solutions.

While WaveVision 5 software (...)

Simulation model

ADC12D1000 IBIS Model

SNAM014.ZIP (41 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

TIDA-00113 — Driving GSPS ADCs in Single-Channel or Dual-Channel Mode for High Bandwidth Applications

This design is intended to help the system designer in understanding tradeoffs and optimizing implementation for driving the Giga-Sample-Per-Second ADC with balun configurations for wideband applications.  The tradeoffs considered include balun construction, insertion loss, dynamic performance (...)
Reference designs

TIDA-00479 — Optimal Clock Sources for GSPS ADCs Reference Design

The ADC12D1600RFRB reference design provides a platform to demonstrate a high speed digitizer application which incorporates clocking, power management, and signal processing. The reference design utilizes the 1.6 GSPS ADC12D1600RF device, onboard FPGA Xilinx Virtex 4, and high performance clock (...)
Reference designs

TIDA-00071 — Schematic and Layout Recommendations for the Giga Sample Per Second (GSPS) ADC

This reference design is a guide to the schematics and layout for the system designer using a GSPS ADC in their system. Use this reference design along with the datasheet — the datasheet is always the final authority. Also, the ADC1xDxxxx(RF)RB Reference Board provides a useful reference (...)
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BGA (NXA) 292 View options

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