8.3.1 Amplitude and Phase Imbalance Correction of Differential Analog Input

The ADC performance can be sensitive to amplitude and phase imbalance of the input differential signal and therefore integrates a front-end balance correction circuit to optimize the second-order distortion (HD2) performance of the ADC in the presence of an imbalanced input signal. 4-bit control of the phase mismatch and 3-bit control of the amplitude mismatch corrects the input mismatch before the input buffer. A simplified diagram of the amplitude and phase correction circuit at the ADC input is shown in Figure 32.

Figure 32. Simplified Input Differential Balance Correction Circuit

Amplitude correction is achieved by varying the single-ended termination resistance of each input while maintaining constant total differential resistance, thereby adjusting the amplitude at each input but leaving the differential swing constant. Phase correction, also considered capacitive balance correction, varies the capacitive load at the ADC input, thereby correcting a phase imbalance by creating a bandwidth difference between the analog inputs that minimally affects amplitude. This function is useful for correcting the balance of transformers or filters that drive the ADC analog inputs. Figure 33 shows the measured HD2 resulting from an example 240-MHz imbalanced signal input into the ADC14X250 device recorded over the available amplitude and phase correction settings, demonstrating the optimization of HD2. Performance parameters in the Electrical Characteristics: Dynamic Converter Performance are characterized with the amplitude and phase correction settings in the default condition.

Figure 33. Gain and Phase Imbalance HD2 Optimization

8.3.2 Input Clock Divider

An input clock divider allows a high frequency clock signal to be distributed throughout the system and locally divided down at the ADC device so that coupling of signals at common intermediate frequencies into other parts of the system can be avoided. The frequency at the CLKIN input may be divided down to the sampling rate of the ADC by factors of 1, 2, 4, or 8. Changing the clock divider setting initiates a JESD204 link re-initialization and requires re-calibration of the ADC if the sampling rate is changed from the rate during the previous calibration.

8.3.3 SYSREF Offset Feature and Detection Gate

When the signal at the SYSREF input is not actively toggling periodically, the SYSREF signal is considered to be in an idle state. The idle state is recommended at any time the ADC14X250 spurious performance must be maximized. When the SYSREF signal is in the idle state for longer than 1 µs, an undesirable offset voltage may build up across the AC coupling capacitors between the SYSREF transmitter and the ADC14X250 device input. This offset voltage creates a signal threshold problem, requires a long time to dissipate, and therefore prevents quick transition of the SYSREF signal out of the idle state. Two features are provided as a solution and are shown in Figure 50, namely the SYSREF offset feature and SYSREF detection gate.

In the case that the SYSREF signal idle state has a 0-V differential value, or if the ADC14X250 device must be insensitive to noise that may appear on the SYSREF signal, then the SYSREF detection gate may be used. The detection gate is the AND gate shown in Figure 50 that enables or disables propagation of the SYSREF signal through to the internal device logic. If the detection gate is disabled and a false edge appears at the SYSREF input, the signal does not disrupt the internal clock alignment. Note that the SYSREF detection gate is disabled by default; therefore, the device does not respond to a SYSREF edge until the detection gate is enabled.

The SYSREF offset and detection gate features are both controlled through the SPI.

8.3.4 DC Offset Correction

DC offset correction is provided using a digital high-pass IIR filter at the immediate output of the ADC core. The DC offset correction is bypassed by default, but may be enabled and configured via the SPI. The 3-dB bandwidth of the IIR digital correction filter may be set to four different low-frequency values. When DC offset correction is enabled, any signal in the stop-band of the high-pass filter is attenuated. The settling time of the DC offset correction is approximately equal to the inverse of the 3-dB bandwidth setting.

8.3.5 Serial Differential Output Drivers

The differential drivers of the ADC14X250 device that output the serial JESD204B data are voltage mode drivers with amplitude control and de-emphasis features that may be configured through the SPI for a variety of different channel applications. Eight amplitude control (VOD) and eight de-emphasis control (DEM) settings are available. Both VOD and DEM register fields must be configured to optimize the noise performance of the serial interface for a particular lossy channel.

The output common-mode of the driver varies with the configuration of the output swing. Therefore, AC coupling is strongly recommended between the ADC14X250 device and the device receiving the serial data.

8.3.5.1 De-Emphasis Equalization

De-emphasis of the differential output is provided as a form of continuous-time linear equalization that imposes a high-pass frequency response onto the output signal to compensate for frequency-dependent attenuation as the signal propagates through the channel to the receiver. In the time-domain, the de-emphasis appears as the bit transition transient followed by an immediate reduction in the differential amplitude, as shown in Figure 34. The characteristic appearance of the waveform changes with differential amplitude and the magnitude of de-emphasis applied. The serial lane rate determines the available period of time during which the de-emphasis transient settles. However, the lane rate does not affect the settling behavior of the applied de-emphasis.

Figure 34. De-emphasis of the Differential Output Signal

Table 1 indicates the typical measured values for the de-emphasis range, where the de-emphasis value is measured as the ratio (in units of [dB]) between the peak voltage after the signal transition to the settled voltage value in one bit period. The data rate for this measurement is 1.2 Gb/s to allow settling of the de-emphasis transient. Table 1 illustrates the actual de-emphasis value in terms of voltage attenuation and shows dependence on the amplitude setting, but does not reflect the optimal amplitude setting (VOD) and de-emphasis setting (DEM) for a particular lossy channel. Table 2 shows the amplitude of the differential signal swing during its settled state after the transition transient. The measurement is performed at 1.2 Gb/s and the units are in differential peak-to-peak mV.

Table 1. De-Emphasis Values (dB) for All VOD and DEM Configuration Settings

		DEM
		0	1	2	3	4	5	6	7
VOD	0	0	–0.2	–1.1	–2.2	–3.0	–4.3	–5.6	–8.5
	1	0	–0.4	–1.7	–2.9	–3.8	–5.1	–6.5	–9.6
	2	0	–0.7	–2.2	–3.5	–4.5	–5.9	–7.4	–10.4
	3	0	–1.0	–2.8	–4.2	–5.2	–6.7	–8.1	–11.2
	4	0	–1.4	–3.4	–4.9	–5.9	–7.4	–8.9	–12.1
	5	0	–1.7	–3.9	–5.5	–6.5	–8.0	–9.5	–12.7
	6	0	–2.1	–4.4	–6.0	–7.1	–8.6	–10.2	–13.4
	7	0	–2.5	–4.9	–6.5	–7.6	–9.2	–10.7	–14.0

Table 2. Settled Differential Voltage Swing Values, VOD (mV-peak-peak) for All VOD and DEM Configuration Settings

		DEM
		0	1	2	3	4	5	6	7
VOD	0	570	550	500	440	400	350	300	210
	1	660	630	550	470	430	370	310	220
	2	750	690	580	500	450	380	320	230
	3	840	750	610	520	460	390	330	230
	4	940	800	630	530	470	400	340	230
	5	1020	840	650	550	480	410	340	240
	6	1110	870	670	560	490	410	340	240
	7	1200	900	680	570	500	420	350	240

8.3.6 ADC Core Calibration

After power-up, the ADC14X250 device detects that the supplies and clock are valid, waits for a power-up delay, and then performs a calibration of the ADC core automatically. The power-up delay is 8.4 × 10⁶ sampling clock cycles or 33.6 ms at a 250-MSPS sampling rate. The calibration requires approximately 1.0 × 10⁶ sampling clock cycles.

If the system requires that the ADC14X250 input clock divider value (CLKDIV) is set to 2, 4, or 8, then ADC calibration must be performed manually after CLKDIV has been set to the desired value. Manual calibration is performed by changing to power down mode, returning to normal operation, and monitoring the CAL_DONE bit in the JESD_STATUS register until calibration is complete. As an alternative to monitoring CAL_DONE, the system may wait 1.5 × 10⁶ sampling clock cycles until calibration is complete.

Re-calibration is not required across the supported operating temperature range to maintain functional performance, but it is recommended for large changes in ambient temperature to maintain optimal dynamic performance. Changing the sampling rate always requires re-calibration of the ADC core. For more information about device modes, see Power-Down and Sleep Modes.

8.3.7 Data Format

Data may be output in the serial stream as 2’s complement format by default or optionally as offset binary. This formatting is configured through the SPI and is performed in the data path prior to JESD204B data framing, scrambling and 8b/10b encoding.

8.3.8 JESD204B Supported Features

The ADC14X250 device supports a feature set of the JESD204B standard targeted to its intended applications but does not implement all the flexibility of the standard. Table 3 summarizes the level of feature support.

8.3.9 Transport Layer Configuration

The transport layer features supported by the ADC14X250 device are a subset of possible features described in the JESD204B standard. The configuration options are intentionally simplified to provide the lowest power and most easy-to-use solution.

8.3.9.2 Frame Format

The format of the data arranged in a frame is fixed. The octets per frame (F), samples per frame (S), and high-density mode (HD) parameters are not independently configurable. The N, N’, CS, CF, M, and HD parameters are fixed and not configurable. Figure 35 shows the data format.

Figure 35. Transport Layer Definitions for the Supported-Lane Configurations

8.3.10 Test Pattern Sequences

The SPI may enable the following test pattern sequences. Short- and long-transport layer, RPAT, and JSPAT sequences are not supported.

8.3.11 JESD204B Link Initialization

A JESD204B link is established via link initialization, which involves the following steps: frame alignment, code group synchronization, and initial lane synchronization. These steps are shown in Figure 36. Link initialization must occur between the transmitting device (ADC14X250) and receiving device before sampled data may be transmitted over the link. The link initialization steps described here are specifically for the ADC14X250 device, supporting JESD204B subclass 1.

Figure 36. Link-initialization Timing and Flow Diagram

Figure 37. Device Start-Up and JESD204B Link Synchronization Flow Chart

The flowchart in Figure 37 describes how the ADC14X250 device initializes the JESD204B link and reacts to changes in the link. After the ADC core calibration is finished, the ADC14X250 device begins with PLL calibration and link initialization using a default frame clock and LMFC alignment by sending K28.5 characters. PLL calibration requires approximately 153×10³ sampling clock cycles. If SYNCb is not asserted, then the device immediately advances to the ILA sequence at the next LMFC boundary. Whereas, if SYNCb is asserted, then the device continues to output K28.5 characters until SYNCb is de-asserted.

When a SYSREF rising edge event is detected, then the ADC14X250 device compares the SYSREF event to the current alignment of the LMFC. If the SYSREF event is aligned to the current LMFC alignment, then no action is taken and the device continues to output data. If misalignment is detected, then the SYSREF event is compared to the frame clock. If misalignment of the frame clock is also detected, then the clocks are re-aligned and the link is re-initialized. If the frame clock is not misaligned, then the frame clock alignment is not updated. In the cases that a SYSREF event causes a link re-initialization, the ADC14X250 device begins sending K28.5 characters without a SYNCb assertion and immediately transitions to the ILA sequence on the next LMFC boundary unless the SYNCb signal is asserted. Anytime the frame clock and LMFC are re-aligned, the serializer PLL must calibrate before code group synchronization begins. SYSREF events must not occur during ADC14X250 device power-up, ADC calibration, or PLL calibration. The JESD_STATUS register is available to check the status of the ADC14X250 device and the JESD204B link.

If a SYNCb assertion is detected for at least 4 frame clock cycles, the ADC14X250 device immediately breaks the link and sends K28.5 characters until the SYNCb signal is de-asserted.

When exiting sleep mode, the frame clock and LMFC are started with a default (unknown) phase alignment, PLL calibration is performed, and the device immediately transitions into sending K28.5 characters.

8.3.12 Sync~ Signal Selection

The JESD204B sync~ signal can be directed to the internal JESD204B core block via two different input paths: via the external pins or SPI. The selection MUX is controlled using the SYNC_SEL register field and sync~ control is performed using the JSYNC_N register field via SPI . By default, the signal is routed from the external SYNCb+/- pins and writes to the JSYNC_N register field are ignored.

Optionally, the signal may be routed via SPI by setting the register field SYNC_SEL = 1. In this mode, signals at the external SYNCb+/- pins are ignored and the sync~ signal is written to the JSYNC_N register field.

8.3.13 SPI

The SPI allows access to the internal configuration registers of the ADC through read and write commands to a specific address. The interface protocol has a 1-bit command, 15-bit address word and 8-bit data word as shown in Figure 38. A read or write command is 24 bits in total, starting with the read or write command bit where 0 indicates a write command and 1 indicates a read command. The read or write command bit is clocked into the device on the first rising edge of SCLK after CSb is asserted to 0. During a write command, the 15-bit address and 8-bit data values follow the read or write bit MSB-first and are latched on the rising edge of SCLK. During a read command, the SDO output is enabled shortly after the 16^th rising edge of SCLK and outputs the read value MSB first before the SDO output is returned to a high impedance state. The read or write command is completed on the SCLK rising edge on which the data word’s LSB is latched. CSb may be de-asserted to 1 after the LSB is latched into the device.

The SPI allows command streaming where multiple commands are made without de-asserting CSb in-between commands. The commands in the stream must be of similar types, either read or write. Each subsequent command applies to the register address adjacent to the register accessed in the previous command. The address order can be configured as either ascending or descending. Command streaming is accomplished by immediately following a completed command with another set of 8 rising edges of SCLK without de-asserting CSb. During a write command, an 8-bit data word is input on the SDI input for each subsequent set of SCLK edges. During a read command, data is output from SDO for each subsequent set of SCLK edges. Each subsequent command is considered finished after the 8^th rising edge of SCLK. De-asserting CSb aborts an incomplete command.

The SDO output is high impedance at all times other than during the final portion of a read command. During the time that the SDO output is active, the logic level is determined by a configuration register. The SPI output logic level must be properly configured after power up and before making a read command to prevent damaging the receiving device or any other device connected to the SPI bus. Until the SPI_CFG register is properly configured, voltages on the SDO output may be as high as the V_A3.0 supply during a read command. The default state of SDO is to output 3 V logic levels during a read command. The SDI, SCLK, and CSB pins are all 1.2-V to 3-V logic compatible.

Figure 38. Serial Interface Protocol

8.4.1 Power-Down and Sleep Modes

Power-down and sleep modes are provided to allow the user to reduce the power consumption of the device without disabling power supplies. Both modes reduce power consumption by the same amount but they differ in the amount of time required to return to normal operation. Upon changing from Power Down back to Normal operation, an ADC calibration routine is performed. Waking from sleep mode does not perform ADC calibration (see ADC Core Calibration for more details). Neither power-down mode nor sleep mode resets configuration registers.

Table 6. ADC14X250 Register Map

8.5.1 Register Descriptions