Product details

Sample rate (Max) (MSPS) 250 Resolution (Bits) 14 Number of input channels 1 Interface type JESD204B Analog input BW (MHz) 800 Features High Performance Rating Catalog Input range (Vp-p) 1.7 Power consumption (Typ) (mW) 584 Architecture Pipeline SNR (dB) 71.1 ENOB (Bits) 11.5 SFDR (dB) 93 Operating temperature range (C) -40 to 85 Input buffer Yes
Sample rate (Max) (MSPS) 250 Resolution (Bits) 14 Number of input channels 1 Interface type JESD204B Analog input BW (MHz) 800 Features High Performance Rating Catalog Input range (Vp-p) 1.7 Power consumption (Typ) (mW) 584 Architecture Pipeline SNR (dB) 71.1 ENOB (Bits) 11.5 SFDR (dB) 93 Operating temperature range (C) -40 to 85 Input buffer Yes
VQFN (RHB) 32 25 mm² 5 x 5
  • Resolution: 14-Bit
  • Conversion Rate: 250 MSPS
  • Performance:
    • Input: 240 MHz, –3 dBFS
      • SNR: 70.1 dBFS
      • Noise Spectral Density: –151.1 dBFS/Hz
      • SFDR: 87 dBFS
      • Non-HD2 and Non-HD3 SPUR: –92 dBFS
    • No Input SNR: 71.1 dBFS
  • Power Dissipation: 584 mW
  • Performance Rated up to 105°C (at thermal pad)
  • JESD204B Subclass 1 Single Lane Serial Data Interface With Lane Rate Up To 5 Gb/s
  • Buffered Analog Inputs
  • Differential Input Phase and Amplitude Correction
  • Input Sampling Clock Divider (Divide-by-1,2,4,8)
  • 4-Wire Serial Peripheral Interface (SPI)
  • 32-Pin WQFN Package (5×5 mm, 0.5-mm Pitch)
  • Resolution: 14-Bit
  • Conversion Rate: 250 MSPS
  • Performance:
    • Input: 240 MHz, –3 dBFS
      • SNR: 70.1 dBFS
      • Noise Spectral Density: –151.1 dBFS/Hz
      • SFDR: 87 dBFS
      • Non-HD2 and Non-HD3 SPUR: –92 dBFS
    • No Input SNR: 71.1 dBFS
  • Power Dissipation: 584 mW
  • Performance Rated up to 105°C (at thermal pad)
  • JESD204B Subclass 1 Single Lane Serial Data Interface With Lane Rate Up To 5 Gb/s
  • Buffered Analog Inputs
  • Differential Input Phase and Amplitude Correction
  • Input Sampling Clock Divider (Divide-by-1,2,4,8)
  • 4-Wire Serial Peripheral Interface (SPI)
  • 32-Pin WQFN Package (5×5 mm, 0.5-mm Pitch)

The ADC14X250 device is a monolithic single-channel high performance analog-to-digital converter capable of converting analog input signals into 14-bit digital words with a sampling rate of 250 MSPS. This converter uses a differential pipelined architecture with integrated input buffer to provide excellent dynamic performance and low power consumption across an extended temperature range from –40°C to 105°C as measured at the device’s PCB footprint thermal pad.

The integrated input buffer eliminates charge kickback noise coming from the internal switched capacitor sampling circuits and eases the system-level design of the driving amplifier, anti-aliasing filter, and impedance matching. The buffer can be also be adjusted to correct for phase and amplitude imbalance of the differential input signal path to improve even order harmonic distortion. An input sampling clock divider provides integer divide ratios to simplify system clocking. An integrated low-noise voltage reference eases board level design without requiring external decoupling capacitors. The output digital data is provided through a JESD204B subclass 1 single lane interface from a 32-pin, 5-mm × 5-mm WQFN package. The ADC14X250 operates on 1.2 V, 1.8 V and 3.0 V power supplies. A SPI is available to configure the device that is compatible with 1.2-V to 3-V logic.

The ADC14X250 device is a monolithic single-channel high performance analog-to-digital converter capable of converting analog input signals into 14-bit digital words with a sampling rate of 250 MSPS. This converter uses a differential pipelined architecture with integrated input buffer to provide excellent dynamic performance and low power consumption across an extended temperature range from –40°C to 105°C as measured at the device’s PCB footprint thermal pad.

The integrated input buffer eliminates charge kickback noise coming from the internal switched capacitor sampling circuits and eases the system-level design of the driving amplifier, anti-aliasing filter, and impedance matching. The buffer can be also be adjusted to correct for phase and amplitude imbalance of the differential input signal path to improve even order harmonic distortion. An input sampling clock divider provides integer divide ratios to simplify system clocking. An integrated low-noise voltage reference eases board level design without requiring external decoupling capacitors. The output digital data is provided through a JESD204B subclass 1 single lane interface from a 32-pin, 5-mm × 5-mm WQFN package. The ADC14X250 operates on 1.2 V, 1.8 V and 3.0 V power supplies. A SPI is available to configure the device that is compatible with 1.2-V to 3-V logic.

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* Data sheet ADC14X250 14-Bit 250 MSPS Single Channel ADC With 5 Gb/s JESD204B Output datasheet (Rev. B) PDF | HTML 19 Apr 2017

Design & development

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Evaluation board

ADC14X250EVM — ADC14X250 Evaluation Module

The ADC14X250EVM is an evaluation board used to evaluate the ADC14X250 analog-to-digital converter (ADC) from Texas Instruments. The ADC14X250 is a single channel 14-bit ADC capable of operating at sampling rates up to 250 Mega Samples Per Second (MSPS) with outputs featuring a standard JESD204B (...)

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Firmware

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Support software

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Simulation model

ADC14X250 IBIS Model

SLAM286.ZIP (38 KB) - IBIS Model
Simulation tool

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VQFN (RHB) 32 View options

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