SBAS716 February   2019 ADC3244E

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Performance at fS = 125 MSPS, fIN = 10 MHz
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: General
    6. 7.6  Electrical Characteristics: AC Performance
    7. 7.7  Digital Characteristics
    8. 7.8  Timing Requirements: General
    9. 7.9  Timing Requirements: LVDS Output
    10. 7.10 Typical Characteristics
    11. 7.11 Typical Characteristics: Contour
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 SNR and Clock Jitter
      3. 9.3.3 Digital Output Interface
        1. 9.3.3.1 One-Wire Interface: 14x Serialization
        2. 9.3.3.2 Two-Wire Interface: 7x Serialization
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Divider
      2. 9.4.2 Chopper Functionality
      3. 9.4.3 Power-Down Control
        1. 9.4.3.1 Improving Wake-Up Time From Global Power-Down
      4. 9.4.4 Internal Dither Algorithm
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 Register Initialization
    6. 9.6 Register Maps
      1. 9.6.1 Summary of Special Mode Registers
      2. 9.6.2 Serial Register Description
        1. 9.6.2.1  Register 01h
          1. Table 10. Register 01h Description
        2. 9.6.2.2  Register 03h
          1. Table 11. Register 03h Description
        3. 9.6.2.3  Register 04h
          1. Table 12. Register 04h Description
        4. 9.6.2.4  Register 05h
          1. Table 13. Register 05h Description
        5. 9.6.2.5  Register 06h
          1. Table 14. Register 06h Description
        6. 9.6.2.6  Register 07h
          1. Table 15. Register 07h Description
        7. 9.6.2.7  Register 09h
          1. Table 16. Register 09h Description
        8. 9.6.2.8  Register 0Ah
          1. Table 17. Register 0Ah Description
        9. 9.6.2.9  Register 0Bh
          1. Table 18. Register 0Bh Description
        10. 9.6.2.10 Register 0Eh
          1. Table 19. Register 0Eh Description
        11. 9.6.2.11 Register 0Fh
          1. Table 20. Register 0Fh Description
        12. 9.6.2.12 Register 13h (address = 13h)
          1. Table 21. Register 13h Field Descriptions
        13. 9.6.2.13 Register 15h
          1. Table 23. Register 15h Description
        14. 9.6.2.14 Register 25h
          1. Table 24. Register 25h Description
        15. 9.6.2.15 Register 27h
          1. Table 26. Register 27h Description
        16. 9.6.2.16 Register 41Dh
          1. Table 27. Register 41Dh Description
        17. 9.6.2.17 Register 422h
          1. Table 28. Register 422h Description
        18. 9.6.2.18 Register 434h
          1. Table 29. Register 434h Description
        19. 9.6.2.19 Register 439h
          1. Table 30. Register 439h Description
        20. 9.6.2.20 Register 51Dh
          1. Table 31. Register 51Dh Description
        21. 9.6.2.21 Register 522h
          1. Table 32. Register 522h Description
        22. 9.6.2.22 Register 534h
          1. Table 33. Register 534h Description
        23. 9.6.2.23 Register 539h
          1. Table 34. Register 539h Description
        24. 9.6.2.24 Register 608h
          1. Table 35. Register 608h Description
        25. 9.6.2.25 Register 70Ah
          1. Table 36. Register 70Ah Description
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Electrical Characteristics: AC Performance

typical values at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted); minimum and maximum values at full temperature range of –50°C to +105°C
PARAMETER TEST CONDITIONS fS = 125 MSPS UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio
(from 1-MHz offset)		 fIN = 10 MHz 72.9 73.3 dBFS
fIN = 70 MHz 71 72.6 73
fIN = 100 MHz 72.4 72.8
fIN = 170 MHz 71.7 72.2
fIN = 230 MHz 71 71.6
Signal-to-noise ratio
(full Nyquist band)		 fIN = 10 MHz 72.5 72.9
fIN = 70 MHz 72.2 72.6
fIN = 100 MHz 72.1 72.5
fIN = 170 MHz 71.4 71.9
fIN = 230 MHz 70.7 71.3
NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –150.8 –151.1 dBFS/Hz
fIN = 70 MHz –150.5 –148.9 –150.9
fIN = 100 MHz –150.3 –150.7
fIN = 170 MHz –149.6 –150.1
fIN = 230 MHz –148.9 –149.5
SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 72.8 73 dBFS
fIN = 70 MHz 69.6 72.6 72.9
fIN = 100 MHz 72.3 72.5
fIN = 170 MHz 71.5 71.9
fIN = 230 MHz 70.7 71.1
ENOB(1) Effective number of bits fIN = 10 MHz 11.8 11.8 Bits
fIN = 70 MHz 11.3 11.8 11.8
fIN = 100 MHz 11.7 11.8
fIN = 170 MHz 11.6 11.6
fIN = 230 MHz 11.5 11.5
SFDR Spurious-free dynamic range fIN = 10 MHz 93 86 dBc
fIN = 70 MHz 82 94 89
fIN = 100 MHz 89 85
fIN = 170 MHz 85 85
fIN = 230 MHz 83 82
HD2 Second-order harmonic distortion fIN = 10 MHz 95 96 dBc
fIN = 70 MHz 82 96 95
fIN = 100 MHz 91 90
fIN = 170 MHz 85 85
fIN = 230 MHz 83 83
HD3 Third-order harmonic distortion fIN = 10 MHz 94 86 dBc
fIN = 70 MHz 83 94 89
fIN = 100 MHz 91 85
fIN = 170 MHz 97 89
fIN = 230 MHz 87 85
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 100 95 dBc
fIN = 70 MHz 86 99 95
fIN = 100 MHz 99 95
fIN = 170 MHz 100 91
fIN = 230 MHz 96 92
THD Total harmonic distortion fIN = 10 MHz 91 85 dBc
fIN = 70 MHz 76 91 86
fIN = 100 MHz 87 83
fIN = 170 MHz 84 82
fIN = 230 MHz 81 80
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 –97 –95 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 –91 –90
(1) Reported from a 1-MHz offset.