SBAS673A July   2014  – October 2015 ADC3421 , ADC3422 , ADC3423 , ADC3424

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: General
    6. 7.6  Electrical Characteristics: ADC3421, ADC3422
    7. 7.7  Electrical Characteristics: ADC3423, ADC3424
    8. 7.8  AC Performance: ADC3421
    9. 7.9  AC Performance: ADC3422
    10. 7.10 AC Performance: ADC3423
    11. 7.11 AC Performance: ADC3424
    12. 7.12 Digital Characteristics
    13. 7.13 Timing Requirements: General
    14. 7.14 Timing Requirements: LVDS Output
    15. 7.15 Typical Characteristics: ADC3421
    16. 7.16 Typical Characteristics: ADC3422
    17. 7.17 Typical Characteristics: ADC3423
    18. 7.18 Typical Characteristics: ADC3424
    19. 7.19 Typical Characteristics: Common
    20. 7.20 Typical Characteristics: Contour
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 SNR and Clock Jitter
      3. 9.3.3 Digital Output Interface
        1. 9.3.3.1 One-Wire Interface: 12x Serialization
        2. 9.3.3.2 Two-Wire Interface: 6x Serialization
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Divider
      2. 9.4.2 Chopper Functionality
      3. 9.4.3 Power-Down Control
      4. 9.4.4 Internal Dither Algorithm
      5. 9.4.5 Summary of Performance Mode Registers
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 Register Initialization
    6. 9.6 Register Maps
      1. 9.6.1 Serial Register Description
        1. 9.6.1.1 Register 13h (address = 13h)
        2. 9.6.1.2 Register 11Dh (address = 11Dh)
        3. 9.6.1.3 Register 21Dh (address = 21Dh)
        4. 9.6.1.4 Register 308h (address = 308h)
        5. 9.6.1.5 Register 41Dh (address = 41Dh)
        6. 9.6.1.6 Register 51Dh (address = 51Dh)
        7. 9.6.1.7 Register 608h (address = 608h)
        8. 9.6.1.8 Register 70Ah (address = 70Ah)
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

RTQ Package
VQFN-56
Top View
ADC3421 ADC3422 ADC3423 ADC3424 Pin_dgm_SBAS670.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AVDD 6, 7, 10, 11, 14, 15, 20, 23, 28, 29, 32, 33, 36 I Analog 1.8-V power supply
CLKM 21 I Negative differential clock input for the ADC
CLKP 22 I Positive differential clock input for the ADC
DA0M 4 O Negative serial LVDS output for wire-0 of channel A
DA0P 3 O Positive serial LVDS output for wire-0 of channel A
DA1M 2 O Negative serial LVDS output for wire-1 of channel A
DA1P 1 O Positive serial LVDS output for wire-1 of channel A
DB0M 56 O Negative serial LVDS output for wire-0 of channel B
DB0P 55 O Positive serial LVDS output for wire-0 of channel B
DB1M 54 O Negative serial LVDS output for wire-1 of channel B
DB1P 53 O Positive serial LVDS output for wire-1 of channel B
DC0M 46 O Negative serial LVDS output for wire-0 of channel C
DC0P 45 O Positive serial LVDS output for wire-0 of channel C
DC1M 44 O Negative serial LVDS output for wire-1 of channel C
DC1P 43 O Positive serial LVDS output for wire-1 of channel C
DD0M 42 O Negative serial LVDS output for wire-0 of channel D
DD0P 41 O Positive serial LVDS output for wire-0 of channel D
DD1M 40 O Negative serial LVDS output for wire-1 of channel D
DD1P 39 O Positive serial LVDS output for wire-1 of channel D
DCLKM 51 O Negative bit clock output
DCLKP 50 O Positive bit clock output
DVDD 5, 38, 47, 52 I Digital 1.8-V power supply
FCLKM 49 O Negative frame clock output
FCLKP 48 O Positive frame clock output
GND PowerPAD™ I Ground, 0 V
INAM 8 I Negative differential analog input for channel A
INAP 9 I Positive differential analog input for channel A
INBM 13 I Negative differential analog input for channel B
INBP 12 I Positive differential analog input for channel B
INCM 30 I Negative differential analog input for channel C
INCP 31 I Positive differential analog input for channel C
INDM 35 I Negative differential analog input for channel D
INDP 34 I Positive differential analog input for channel D
PDN 37 I Power-down control. This pin can be configured via the SPI. This pin has an internal 150-kΩ pulldown resistor.
RESET 24 I Hardware reset; active high. This pin has an internal 150-kΩ pulldown resistor.
SCLK 16 I Serial interface clock input. This pin has an internal 150-kΩ pulldown resistor.
SDATA 17 I Serial interface data input. This pin has an internal 150-kΩ pulldown resistor.
SDOUT 19 O Serial interface data output
SEN 18 I Serial interface enable; active low.
This pin has an internal 150-kΩ pullup resistor to AVDD.
SYSREFM 26 I Negative external SYSREF input
SYSREFP 25 I Positive external SYSREF input
VCM 27 O Common-mode voltage for analog inputs