SBASAI7 March 2023 ADC34RF52
PRODUCTION DATA
To maximize the SNR performance of the ADC a low jitter (< 50 fs) sampling clock is required. #FIG_ETT_TT3_NPB shows the estimated SNR performance vs input frequency vs external clock jitter. The internal ADC aperture jitter also has some dependency to the clock amplitude (gets more sensitive with higher input frequency) as shown in #FIG_GTT_TT3_NPB.
When using averaging and/or decimation, the SNR for a single ADC core is estimated before adding the SNR improvement from internal averaging and/or decimation.