The following screen shot shows the top layer of the ADC366x/368x EVM.
- Signal and clock inputs are routed as differential signals on the top layer avoiding vias.
- SLVDS output interface lanes are routed differential and length matched
- Bypass caps are close to the VREF pin on the top layer avoiding vias.
Figure 11-1 Layout example: top layer of ADC366x/368x EVM