SBAS991 February 2021 ADC3663
The ADC366x includes a register (DLL PDN (0x11, D2) which increases the signal acquisition time window for clock rates below 40 MSPS from 25% to 50% of the clock period. Increasing the sampling time provides a longer time for the driving amplifier to settle out the signal which can improve the SNR performance of the system. This register should only be used for the 65 MSPS speed grade (ADC3663) For the 10 and 25 MSPS device speed grades the sampling time is already set to TS/2. When powering down the DLL, the acquisition time will track the clock duty cycle (50% is recommended).
|SAMPLING CLOCK FS (MSPS)||DLL PDN (0x11, D2)||ACQUISITION TIME (tACQ)|
|65||0||TS / 4|
|≤ 40||1||TS / 2|