SBAS607B April   2016  – September 2016 ADS127L01

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Serial Interface
    7. 6.7  Switching Characteristics: Serial Interface Mode
    8. 6.8  Timing Requirements: Frame-Sync Master Mode
    9. 6.9  Switching Characteristics: Frame-Sync Master Mode
    10. 6.10 Timing Requirements: Frame-Sync Slave Mode
    11. 6.11 Switching Characteristics: Frame-Sync Slave Mode
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs (AINP, AINN)
      2. 8.3.2 Digital Filter
        1. 8.3.2.1 Low-Latency Filter
          1. 8.3.2.1.1 Low-Latency Filter Frequency Response
          2. 8.3.2.1.2 Low-Latency Filter Settling Time
        2. 8.3.2.2 Wideband Filter
          1. 8.3.2.2.1 Wideband Filters Frequency Response
          2. 8.3.2.2.2 Wideband Filters Settling Time
      3. 8.3.3 Voltage Reference Inputs (REFP, REFN)
      4. 8.3.4 Clock Input (CLK)
      5. 8.3.5 Out-of-Range-Detect System Monitor
      6. 8.3.6 System Calibration
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes (HR, LP, VLP)
      2. 8.4.2 Hardware Mode Pins
        1. 8.4.2.1 Interface Selection Pins (FORMAT, FSMODE)
        2. 8.4.2.2 Digital-Filter Path Selection Pins (FILTER[1:0])
        3. 8.4.2.3 Oversampling Ratio Selection Pins (OSR[1:0])
      3. 8.4.3 Start Pin (START)
      4. 8.4.4 Reset and Power-Down Pin (RESET/PWDN)
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI) Programming
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Ready (DRDY/FSYNC)
        4. 8.5.1.4 Data Input (DIN)
        5. 8.5.1.5 Data Output (DOUT)
        6. 8.5.1.6 Daisy-Chain Input (DAISYIN)
        7. 8.5.1.7 SPI Timeout
        8. 8.5.1.8 SPI Commands
          1. 8.5.1.8.1 RESET (0000 011x)
          2. 8.5.1.8.2 START (0000 100x)
          3. 8.5.1.8.3 STOP (0000 101x)
          4. 8.5.1.8.4 RDATA (0001 0010)
          5. 8.5.1.8.5 RREG (0010 rrrr 0000 nnnn)
          6. 8.5.1.8.6 WREG (0100 rrrr 0000 nnnn)
      2. 8.5.2 Frame-Sync Programming
        1. 8.5.2.1 Frame-Sync Master Mode
          1. 8.5.2.1.1 Chip Select (CS) in Frame-Sync Master Mode
          2. 8.5.2.1.2 Serial Clock (SCLK) in Frame-Sync Master Mode
          3. 8.5.2.1.3 Frame-Sync (DRDY/FSYNC) in Frame-Sync Master Mode
          4. 8.5.2.1.4 Data Input (DIN) in Frame-Sync Master Mode
          5. 8.5.2.1.5 Data Output (DOUT) in Frame-Sync Master Mode
          6. 8.5.2.1.6 Daisy-Chain Input (DAISYIN) in Frame-Sync Master Mode
        2. 8.5.2.2 Frame-Sync Slave Mode
          1. 8.5.2.2.1 Chip Select (CS) in Frame-Sync Slave Mode
          2. 8.5.2.2.2 Serial Clock (SCLK) in Frame-Sync Slave Mode
          3. 8.5.2.2.3 Frame-Sync (DRDY/FSYNC) in Frame-Sync Slave Mode
          4. 8.5.2.2.4 Data Input (DIN) in Frame-Sync Slave Mode
          5. 8.5.2.2.5 Data Output (DOUT) in Frame-Sync Slave Mode
          6. 8.5.2.2.6 Daisy-Chain Input (DAISYIN) in Frame-Sync Slave Mode
      3. 8.5.3 Data Format
      4. 8.5.4 Status Word
      5. 8.5.5 Cyclic Redundancy Check (CRC)
        1. 8.5.5.1 Computing the CRC
    6. 8.6 Register Maps
      1. 8.6.1 ID: ID Control Register (address = 00h) [reset = x3h]
      2. 8.6.2 CONFIG: ADC Configuration Register (address = 01h) [reset = 00h]
      3. 8.6.3 OFC0: System Offset Calibration Register 0 (address = 02h) [reset = 00h]
      4. 8.6.4 OFC1: System Offset Calibration Register 1 (address = 03h) [reset = 00h]
      5. 8.6.5 OFC2: System Offset Calibration Register 2 (address = 04h) [reset = 00h]
      6. 8.6.6 FSC0: System Gain Calibration Register 0 (address = 05h) [reset = 00h]
      7. 8.6.7 FSC1: System Gain Calibration Register 1 (address = 06h) [reset = 80h]
      8. 8.6.8 MODE: Mode Settings (address = 07h) [reset = xxh]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Multiple Device Configuration
        1. 9.1.2.1 Cascaded Configuration
          1. 9.1.2.1.1 SPI interface Mode
          2. 9.1.2.1.2 Frame-Sync interface Mode
        2. 9.1.2.2 Daisy-Chain Configuration
          1. 9.1.2.2.1 Daisy-Chain Operation Using SPI interface Mode
          2. 9.1.2.2.2 Daisy-Chain Operation Using Frame-Sync interface Mode
        3. 9.1.2.3 Synchronizing Devices
      3. 9.1.3 ADC Input Driver
        1. 9.1.3.1 Antialiasing Filter
        2. 9.1.3.2 Input Driver Selection
        3. 9.1.3.3 Amplifier Stability
      4. 9.1.4 Modulator Saturation
      5. 9.1.5 ADC Reference Driver
        1. 9.1.5.1 Single Chip Solution: REF6xxx
        2. 9.1.5.2 Multichip Solution: REF50xx + OPA320
      6. 9.1.6 Driving LVDD With an External Supply
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Setup
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Sequencing
    2. 10.2 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

SPI is a trademark of Motorola, Inc.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

esds-image

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.