SBAS607B April   2016  – September 2016 ADS127L01


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Serial Interface
    7. 6.7  Switching Characteristics: Serial Interface Mode
    8. 6.8  Timing Requirements: Frame-Sync Master Mode
    9. 6.9  Switching Characteristics: Frame-Sync Master Mode
    10. 6.10 Timing Requirements: Frame-Sync Slave Mode
    11. 6.11 Switching Characteristics: Frame-Sync Slave Mode
    12. 6.12 Typical Characteristics
  7. Parameter Measurement information
    1. 7.1 Noise Performance
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs (AINP, AINN)
      2. 8.3.2 Digital Filter
        1. Low-Latency Filter
          1. Low-Latency Filter Frequency Response
          2. Low-Latency Filter Settling Time
        2. Wideband Filter
          1. Wideband Filters Frequency Response
          2. Wideband Filters Settling Time
      3. 8.3.3 Voltage Reference Inputs (REFP, REFN)
      4. 8.3.4 Clock Input (CLK)
      5. 8.3.5 Out-of-Range-Detect System Monitor
      6. 8.3.6 System Calibration
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes (HR, LP, VLP)
      2. 8.4.2 Hardware Mode Pins
        1. Interface Selection Pins (FORMAT, FSMODE)
        2. Digital-Filter Path Selection Pins (FILTER[1:0])
        3. Oversampling Ratio Selection Pins (OSR[1:0])
      3. 8.4.3 Start Pin (START)
      4. 8.4.4 Reset and Power-Down Pin (RESET/PWDN)
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI) Programming
        1. Chip Select (CS)
        2. Serial Clock (SCLK)
        3. Data Ready (DRDY/FSYNC)
        4. Data Input (DIN)
        5. Data Output (DOUT)
        6. Daisy-Chain Input (DAISYIN)
        7. SPI Timeout
        8. SPI Commands
          1. RESET (0000 011x)
          2. START (0000 100x)
          3. STOP (0000 101x)
          4. RDATA (0001 0010)
          5. RREG (0010 rrrr 0000 nnnn)
          6. WREG (0100 rrrr 0000 nnnn)
      2. 8.5.2 Frame-Sync Programming
        1. Frame-Sync Master Mode
          1. Chip Select (CS) in Frame-Sync Master Mode
          2. Serial Clock (SCLK) in Frame-Sync Master Mode
          3. Frame-Sync (DRDY/FSYNC) in Frame-Sync Master Mode
          4. Data Input (DIN) in Frame-Sync Master Mode
          5. Data Output (DOUT) in Frame-Sync Master Mode
          6. Daisy-Chain Input (DAISYIN) in Frame-Sync Master Mode
        2. Frame-Sync Slave Mode
          1. Chip Select (CS) in Frame-Sync Slave Mode
          2. Serial Clock (SCLK) in Frame-Sync Slave Mode
          3. Frame-Sync (DRDY/FSYNC) in Frame-Sync Slave Mode
          4. Data Input (DIN) in Frame-Sync Slave Mode
          5. Data Output (DOUT) in Frame-Sync Slave Mode
          6. Daisy-Chain Input (DAISYIN) in Frame-Sync Slave Mode
      3. 8.5.3 Data Format
      4. 8.5.4 Status Word
      5. 8.5.5 Cyclic Redundancy Check (CRC)
        1. Computing the CRC
    6. 8.6 Register Maps
      1. 8.6.1 ID: ID Control Register (address = 00h) [reset = x3h]
      2. 8.6.2 CONFIG: ADC Configuration Register (address = 01h) [reset = 00h]
      3. 8.6.3 OFC0: System Offset Calibration Register 0 (address = 02h) [reset = 00h]
      4. 8.6.4 OFC1: System Offset Calibration Register 1 (address = 03h) [reset = 00h]
      5. 8.6.5 OFC2: System Offset Calibration Register 2 (address = 04h) [reset = 00h]
      6. 8.6.6 FSC0: System Gain Calibration Register 0 (address = 05h) [reset = 00h]
      7. 8.6.7 FSC1: System Gain Calibration Register 1 (address = 06h) [reset = 80h]
      8. 8.6.8 MODE: Mode Settings (address = 07h) [reset = xxh]
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Multiple Device Configuration
        1. Cascaded Configuration
          1. SPI interface Mode
          2. Frame-Sync interface Mode
        2. Daisy-Chain Configuration
          1. Daisy-Chain Operation Using SPI interface Mode
          2. Daisy-Chain Operation Using Frame-Sync interface Mode
        3. Synchronizing Devices
      3. 9.1.3 ADC Input Driver
        1. Antialiasing Filter
        2. Input Driver Selection
        3. Amplifier Stability
      4. 9.1.4 Modulator Saturation
      5. 9.1.5 ADC Reference Driver
        1. Single Chip Solution: REF6xxx
        2. Multichip Solution: REF50xx + OPA320
      6. 9.1.6 Driving LVDD With an External Supply
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Setup
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Sequencing
    2. 10.2 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

TI recommends employing best design practices when laying out a printed-circuit board (PCB) for both analog and digital components. This recommendation generally means that the layout separates analog components [such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog multiplexers] from digital components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio-frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching regulators]. An example of good component placement is shown in Figure 130. Although Figure 130 provides a good example of component placement, the best placement for each application is unique to the geometries, components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every design, and careful consideration must always be used when designing with any analog component.

ADS127L01 system_comp_plcmt_sbas607.gif Figure 130. System Component Placement

The following bullet items outline some basic recommendations for the layout of the ADS127L01 to get the best possible performance of the ADC. A good design can be ruined with bad circuit layout.

  • Separate analog and digital signals. To start, partition the board into analog and digital sections where the layout permits. Route digital traces away from analog traces. This separation prevents digital noise from coupling back into analog signals.
  • The ground plane can be split into an analog plane (AGND) and digital plane (DGND), but this split is not necessary. Place analog signals over the analog plane and digital signals over the digital plane. As a final step in the layout, completely remove the split between the analog and digital grounds. If ground plane separation is necessary, make the connection between AGND and DGND as close to the ADC as possible.
  • Fill void areas on signal layers with ground fill.
  • Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground plane is cut or has other traces that block the current from flowing right next to the signal trace, the return current must find another path to return to the source and complete the circuit. If the return current is forced into a larger path, the chance is increased that the signal will radiate. Sensitive signals are more susceptible to EMI interference.
  • Use bypass capacitors on power supplies to reduce high-frequency noise. Do not place vias between bypass capacitors and the active device. Flow the supply current through the bypass capacitor pins first and then to the ADC supply pins. Placing the bypass capacitors on the same layer close to the active device yields the best results. If multiple ADCs are on the same PCB, use wide power-supply traces or dedicated power-supply planes to minimize the potential of crosstalk between ADCs.
  • Consider the resistance and inductance of the routing. Often, traces for the inputs have resistances that react with the input bias current and cause an added error voltage. Reducing the loop area enclosed by the source signal and the return current reduces the inductance in the path. Reducing the inductance reduces the EMI pickup and the high-frequency impedance seen by the device.
  • Watch for parasitic thermocouples in the layout. Dissimilar metals going from each analog input to the sensor may create a parasitic thermocouple that can add an offset to the measurement. Match the differential inputs for both inputs going to the measurement source.
  • Analog inputs with differential connections must have a capacitor placed differentially across the inputs. The differential capacitors must be high quality. The best ceramic chip capacitors are C0G (NP0), with both stable properties and low noise characteristics.
  • When REFN is tied to AGND, run the two traces separately as a star connection back to the AGND pin in order to minimize coupling between the power-supply trace and reference-return trace.
  • It is important that the clock inputs are free from noise and glitches. Even with relatively slow clock frequencies, short digital-signal rise-and-fall times can cause excessive ringing and noise. For best performance, keep the digital signal traces short, use termination resistors as needed, and make sure all digital signals are routed directly above the ground plane with minimal use of vias.

11.2 Layout Example

Figure 131 is an example layout of the ADS127L01, input driver circuit, and reference driver circuit using four PCB layers. In this example, the top and bottom layers are used for analog and digital signals. The first inner layer is dedicated to the ground plane and the second inner layer is dedicated to the power supplies. The PCB is partitioned with analog signals routed on the left, and digital signals routed on the right. Polygon pours are used to provide low-impedance connections between the power supplies and the reference voltage for the ADC.

ADS127L01 apps_recLayout_sbas607.gif Figure 131. Layout Example