Each channel of the ADS1291, ADS1292, and ADS1292R has a 24-bit ΔΣ ADC. This converter uses a second-order modulator optimized for low-power applications. The modulator samples the input signal at the rate of fMOD = fCLK / 4 or fCLK / 16, as determined by the CLK_DIV bit. In both cases, the sampling clock has a typical value of 128 kHz. As in the case of any ΔΣ modulator, the ADS1291, ADS1292, and ADS1292R noise is shaped until fMOD / 2, as shown in Figure 24. The on-chip digital decimation filters explained in the Digital Decimation Filter section can be used to filter out the noise at higher frequencies. These on-chip decimation filters also provide antialias filtering. This feature of the ΔΣ converters drastically reduces the complexity of analog antialiasing filters that are typically needed with nyquist ADCs.