SBAS459K January   2010  – August 2015 ADS1294 , ADS1294R , ADS1296 , ADS1296R , ADS1298 , ADS1298R


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Switching Characteristics: Serial Interface
    8. 7.8 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Noise Measurements
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Functionality
        1. EMI Filter
        2. Analog Input Structure
        3. Input Multiplexer
          1. Device Noise Measurements
          2. Test Signals (TestP and TestN)
          3. Auxiliary Differential Input (TESTP_PACE_OUT1, TESTN_PACE_OUT2)
          4. Temperature Sensor (TempP, TempN)
          5. Supply Measurements (MVDDP, MVDDN)
          6. Lead-Off Excitation Signals (LoffP, LoffN)
          7. Auxiliary Single-Ended Input
        4. Analog Input
        5. PGA Settings and Input Range
          1. Input Common-Mode Range
          2. Input Differential Dynamic Range
          3. ADC Delta-Sigma Modulator
        6. Reference
        7. ECG-Specific Functions
          1. Input Multiplexer (Rerouting The Right Leg Drive Signal)
          2. Input Multiplexer (Measuring The Right Leg Drive Signal)
          3. Wilson Central Terminal (WCT) and Chest Leads
            1. Augmented Leads
            2. Right Leg Drive with the WCT Point
          4. Lead-Off Detection
            1. DC Lead-Off
            2. AC Lead-Off
          5. RLD Lead-Off
          6. Right Leg Drive (RLD) DC Bias Circuit
            1. WCT as RLD
            2. RLD Configuration with Multiple Devices
          7. Pace Detect
            1. Software Approach
            2. External Hardware Approach
          8. Respiration
            1. External Respiration Circuitry (RESP_CTRL = 01b)
            2. Internal Respiration Circuitry with Internal Clock (RESP_CTRL = 10b, ADS129xR Only)
            3. Internal Respiration Circuitry With User-Generated Signals (RESP_CTRL = 11b, ADS129xR Only)
      2. 9.3.2 Digital Functionality
        1. GPIO Pins (GPIO[4:1])
        2. Power-Down Pin (PWDN)
        3. Reset (RESET Pin and Reset Command)
        4. Digital Decimation Filter
          1. Sinc Filter Stage (sinx / x)
        5. Clock
    4. 9.4 Device Functional Modes
      1. 9.4.1 Data Acquisition
        1. Start Mode
          1. Settling Time
        2. Data Ready Pin (DRDY)
        3. Data Retrieval
          1. Status Word
          2. Readback Length
          3. Data Format
        4. Single-Shot Mode
        5. Continuous Conversion Mode
      2. 9.4.2 Multiple-Device Configuration
        1. Cascade Configuration
        2. Daisy-Chain Configuration
    5. 9.5 Programming
      1. 9.5.1 SPI Interface
        1. Chip Select Pin (CS)
        2. Serial Clock (SCLK)
          1. SCLK Clocking Methods
        3. Data Input Pin (DIN)
        4. Data Output Pin (DOUT)
      2. 9.5.2 SPI Command Definitions
        1.  WAKEUP: Exit Standby Mode
        2.  STANDBY: Enter Standby Mode
        3.  RESET: Reset Registers to Default Values
        4.  START: Start Conversions
        5.  STOP: Stop Conversions
        6.  RDATAC: Read Data Continuous
        7.  SDATAC: Stop Read Data Continuous
        8.  RDATA: Read Data
        9.  Sending Multibyte Commands
        10. RREG: Read From Register
        11. WREG: Write to Register
    6. 9.6 Register Maps
      1. 9.6.1 Register Descriptions
        1.  ID: ID Control Register (address = 00h) (reset = xxh)
        2.  CONFIG1: Configuration Register 1 (address = 01h) (reset = 06h)
        3.  CONFIG2: Configuration Register 2 (address = 02h) (reset = 40h)
        4.  CONFIG3: Configuration Register 3 (address = 03h) (reset = 40h)
        5.  LOFF: Lead-Off Control Register (address = 04h) (reset = 00h)
        6.  CHnSET: Individual Channel Settings (n = 1 to 8) (address = 05h to 0Ch) (reset = 00h)
        7.  RLD_SENSP: RLD Positive Signal Derivation Register (address = 0Dh) (reset = 00h)
        8.  RLD_SENSN: RLD Negative Signal Derivation Register (address = 0Eh) (reset = 00h)
        9.  LOFF_SENSP: Positive Signal Lead-Off Detection Register (address = 0Fh) (reset = 00h)
        10. LOFF_SENSN: Negative Signal Lead-Off Detection Register (address = 10h) (reset = 00h)
        11. LOFF_FLIP: Lead-Off Flip Register (address = 11h) (reset = 00h)
        12. LOFF_STATP: Lead-Off Positive Signal Status Register (address = 12h) (reset = 00h)
        13. LOFF_STATN: Lead-Off Negative Signal Status Register (address = 13h) (reset = 00h)
        14. GPIO: General-Purpose I/O Register (address = 14h) (reset = 0Fh)
        15. PACE: Pace Detect Register (address = 15h) (reset = 00h)
        16. RESP: Respiration Control Register (address = 16h) (reset = 00h)
        17. CONFIG4: Configuration Register 4 (address = 17h) (reset = 00h)
        18. WCT1: Wilson Central Terminal and Augmented Lead Control Register (address = 18h) (reset = 00h)
        19. WCT2: Wilson Central Terminal Control Register (address = 18h) (reset = 00h)
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Setting the Device for Basic Data Capture
        1. Lead-Off
        2. Right Leg Drive
        3. Pace Detection
      2. 10.1.2 Establishing the Input Common-Mode
      3. 10.1.3 Antialiasing
    2. 10.2 Typical Applications
      1. 10.2.1 ADS129xR Respiration Measurement Using Internal Modulation Circuitry
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      2. 10.2.2 Software-Based Artificial Pacemaker Detection Using the PACEOUT Pins on the ADS129x
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power-Up Sequencing
    2. 11.2 Connecting to Unipolar (3 V or 1.8 V) Supplies
    3. 11.3 Connecting to Bipolar (±1.5 V or ±1.8 V) Supplies
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Eight Low-Noise PGAs and Eight High-Resolution ADCs (ADS1298, ADS1298R)
  • Low Power: 0.75 mW/channel
  • Input-Referred Noise: 4 μVPP (150 Hz BW, G = 6)
  • Input Bias Current: 200 pA
  • Data Rate: 250 SPS to 32 kSPS
  • CMRR: –115 dB
  • Programmable Gain: 1, 2, 3, 4, 6, 8, or 12
  • Supports systems meeting AAMI EC11, EC13, IEC60601-1, IEC60601-2-27, and IEC60601-2-51 Standards
  • Unipolar or Bipolar Supplies:
    • AVDD = 2.7 V to 5.25 V
    • DVDD = 1.65 V to 3.6 V
  • Built-In Right Leg Drive Amplifier, Lead-Off Detection, Wilson Center Terminal, Pace Detection, Test Signals
  • Integrated Respiration Impedance Measurement
  • Digital Pace Detection Capability
  • Built-In Oscillator and Reference
  • SPI™-Compatible Serial Interface

2 Applications

  • Medical Instrumentation (ECG, EMG, and EEG):
    Patient Monitoring; Holter, Event, Stress, and Vital Signs Including ECG, AED, Telemedicine
    Bispectral Index (BIS), Evoked Audio Potential (EAP), Sleep Study Monitor

Simplified Schematic

ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R fbd_sbas459.gif

3 Description

The ADS1294, ADS1296, ADS1298 (ADS129x) and ADS1294R, ADS1296R ADS1298R (ADS129xR) are a family of multichannel, simultaneous sampling,
24-bit, delta-sigma (ΔΣ) analog-to-digital converters (ADCs) with built-in programmable gain amplifiers (PGAs), internal reference, and an onboard oscillator. The ADS129x and ADS129xR incorporate all of the features that are commonly required in medical electrocardiogram (ECG) and electroencephalogram (EEG) applications. With high levels of integration and exceptional performance, the ADS129x and ADS129xR enables the development of scalable medical instrumentation systems at significantly reduced size, power, and overall cost.

The ADS129x and ADS129xR have a flexible input multiplexer (mux) per channel that can be independently connected to the internally-generated signals for test, temperature, and lead-off detection. Additionally, any configuration of input channels can be selected for derivation of the right leg drive (RLD) output signal. The ADS129x and ADS129xR operate at data rates as high as 32 kSPS, thereby allowing the implementation of software pace detection. Lead-off detection can be implemented internal to the device, either with a pullup or pulldown resistor, or an excitation current sink or source. Three integrated amplifiers generate the Wilson central terminal (WCT) and the Goldberger central terminals (GCT) required for a standard 12-lead ECG. The ADS129xR versions include a fully integrated, respiration impedance measurement function. Multiple ADS129x and ADS129xR devices can be cascaded in high channel count systems in a daisy-chain configuration.

Package options include a tiny 8-mm × 8-mm,
64-ball BGA, and a TQFP-64. The ADS129x BGA version is specified over the commercial temperature range of 0°C to 70°C. The ADS129xR BGA and ADS129x TQFP versions are specified over the industrial temperature range of –40°C to +85°C.

Device Information(1)

ADS129x, ADS129xR NFBGA (64) 8.00 mm × 8.00 mm
TQFP (64) 10.00 mm × 10.00 mm
  1. For all available packages, see the package option addendum at the end of the data sheet.

4 Revision History

Changes from J Revision (January 2014) to K Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Changed text throughout data sheet for clarityGo
  • Added note to DAISY_IN pin Go
  • Added note to DAISY_IN pin Go
  • Changed Equation 3Go

Changes from I Revision (January 2012) to J Revision

  • Changed NC pin discription in Pin Assignments tableGo
  • Changed NC pin discription in Pin Assignments tableGo
  • Changed order of subsections in the Theory of Operation sectionGo
  • Changed single-ended input description to correct input range valuesGo
  • Changed Figure 27 to show correct input range for single-ended inputsGo
  • Changed Figure 28 to show correct input range for single-ended inputsGo
  • Deleted text regarding large scale signalGo
  • Changed Figure 32 to provide a more stable external reference driver circuitGo
  • Updated Figure 57Go
  • Added Figure 58Go
  • Added discussion of SCLK/DRDY bus behavior to Data Ready (DRDY) sectionGo
  • Added Figure 60Go
  • Added status Word section and Figure 61 to discuss the status wordGo
  • Added Readback Length sectionGo
  • Added SCLK Clocking Methods sectionGo
  • Changed units in TEST_AMP bit description in CONFIG2 registerGo
  • Changed Figure 93 to clarify Initial Flow at Power-UpGo
  • Changed Power-Up Sequencing section text to clarify start-up timingGo
  • Changed Figure 105Go
  • Changed power-up reset wait time in Table 38Go

Changes from H Revision (October 2011) to I Revision

  • Added eighth Features bullet (list of standards supported)Go
  • Updated BGA pin outGo
  • Deleted duplicate Digital input voltage and Digital output voltage rows from Absolute Maximum Ratings tableGo
  • Changed parameter name of Channel Performance, Common-mode rejection ratio and Power-supply rejection ratio parameters in Electrical Characteristics tableGo
  • Updated Functional Block DiagramGo
  • Updated description of Analog Input sectionGo
  • Updated Figure 30Go
  • Updated Figure 33Go
  • Updated Figure 34Go
  • Changed description of START pin in START sectionGo
  • Changed description of Data Ready (DRDY) sectionGo
  • Changed conversion description in Single-Shot Mode sectionGo
  • Changed conversion description in Continuous Mode sectionGo
  • Changed Unit column in Table 14Go
  • Added power-down recommendation to bit 7 description of CHnSET: Individual Channel Settings sectionGo
  • Changed description of bit 5 in RESP: Respiration Control Register sectionGo
  • Corrected name of bit 6 in WCT2: Wilson Central Terminal Control Register sectionGo

Changes from G Revision (February 2011) to H Revision

  • Changed footnote 1 of BGA Pin Assignments tableGo
  • Added footnote 1 cross-reference to RLDIN, TESTP_PACE_OUT1, and TESTP_PACE_OUT in BGA Pin Assignments tableGo
  • Changed footnote 1 of PAG Pin Assignments tableGo
  • Added footnote 1 cross-reference to TESTP_PACE_OUT1, TESTP_PACE_OUT2, and RLDIN in PAG Pin Assignments tableGo
  • Changed description of AVSS and AVDD in PAG Pin Assignments tableGo
  • Added (ADS1298) to High-Resolution mode and Low-Power mode test conditions of Supply Current section in Electrical Characteristics tableGo
  • Changed 3-V Power Dissipation, Quiescent channel power test conditions in Electrical Characteristics tableGo
  • Changed 5-V Power Dissipation, Quiescent channel power test conditions in Electrical Characteristics tableGo
  • Changed title of Figure 20Go
  • Updated Figure 42Go
  • Added new paragraph to Respiration sectionGo
  • Updated Equation 5Go
  • Changed title of Table 13Go
  • Updated Figure 66Go
  • Changed description of STANDBY: Enter STANDBY Mode sectionGo
  • Changed bit name for bits 5, 6, and 7 in ID register of Table 16Go
  • Changed bit name for bits 5, 6, and 7 in ID: ID Control Register sectionGo
  • Added footnote to Figure 97Go
  • Changed description of solid ceramic capacitor in Power Supplies and Grounding sectionGo
  • Changed description of Connecting the Device to Bipolar (±1.5 V/1.8 V) Supplies sectionGo

Changes from F Revision (October 2010) to G Revision

  • Updated entire document to include ADS1294R, ADS1296R, and ADS1298R devicesGo
  • Added CONFIG2.WCT_CHOP bit functionality to Wilson Central Terminal (WCT) and Chest Leads sectionGo
  • Added CONFIG2.WCT_CHOP bit functionality to CONFIG2: Configuration Register 2Go
  • Corrected TEST_PACE_OUT1 and TEST_PACE_OUT2 description in PACE: PACE Detect RegisterGo