SBAS459K January   2010  – August 2015 ADS1294 , ADS1294R , ADS1296 , ADS1296R , ADS1298 , ADS1298R

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Switching Characteristics: Serial Interface
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Measurements
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Functionality
        1. 9.3.1.1 EMI Filter
        2. 9.3.1.2 Analog Input Structure
        3. 9.3.1.3 Input Multiplexer
          1. 9.3.1.3.1 Device Noise Measurements
          2. 9.3.1.3.2 Test Signals (TestP and TestN)
          3. 9.3.1.3.3 Auxiliary Differential Input (TESTP_PACE_OUT1, TESTN_PACE_OUT2)
          4. 9.3.1.3.4 Temperature Sensor (TempP, TempN)
          5. 9.3.1.3.5 Supply Measurements (MVDDP, MVDDN)
          6. 9.3.1.3.6 Lead-Off Excitation Signals (LoffP, LoffN)
          7. 9.3.1.3.7 Auxiliary Single-Ended Input
        4. 9.3.1.4 Analog Input
        5. 9.3.1.5 PGA Settings and Input Range
          1. 9.3.1.5.1 Input Common-Mode Range
          2. 9.3.1.5.2 Input Differential Dynamic Range
          3. 9.3.1.5.3 ADC Delta-Sigma Modulator
        6. 9.3.1.6 Reference
        7. 9.3.1.7 ECG-Specific Functions
          1. 9.3.1.7.1 Input Multiplexer (Rerouting The Right Leg Drive Signal)
          2. 9.3.1.7.2 Input Multiplexer (Measuring The Right Leg Drive Signal)
          3. 9.3.1.7.3 Wilson Central Terminal (WCT) and Chest Leads
            1. 9.3.1.7.3.1 Augmented Leads
            2. 9.3.1.7.3.2 Right Leg Drive with the WCT Point
          4. 9.3.1.7.4 Lead-Off Detection
            1. 9.3.1.7.4.1 DC Lead-Off
            2. 9.3.1.7.4.2 AC Lead-Off
          5. 9.3.1.7.5 RLD Lead-Off
          6. 9.3.1.7.6 Right Leg Drive (RLD) DC Bias Circuit
            1. 9.3.1.7.6.1 WCT as RLD
            2. 9.3.1.7.6.2 RLD Configuration with Multiple Devices
          7. 9.3.1.7.7 Pace Detect
            1. 9.3.1.7.7.1 Software Approach
            2. 9.3.1.7.7.2 External Hardware Approach
          8. 9.3.1.7.8 Respiration
            1. 9.3.1.7.8.1 External Respiration Circuitry (RESP_CTRL = 01b)
            2. 9.3.1.7.8.2 Internal Respiration Circuitry with Internal Clock (RESP_CTRL = 10b, ADS129xR Only)
            3. 9.3.1.7.8.3 Internal Respiration Circuitry With User-Generated Signals (RESP_CTRL = 11b, ADS129xR Only)
      2. 9.3.2 Digital Functionality
        1. 9.3.2.1 GPIO Pins (GPIO[4:1])
        2. 9.3.2.2 Power-Down Pin (PWDN)
        3. 9.3.2.3 Reset (RESET Pin and Reset Command)
        4. 9.3.2.4 Digital Decimation Filter
          1. 9.3.2.4.1 Sinc Filter Stage (sinx / x)
        5. 9.3.2.5 Clock
    4. 9.4 Device Functional Modes
      1. 9.4.1 Data Acquisition
        1. 9.4.1.1 Start Mode
          1. 9.4.1.1.1 Settling Time
        2. 9.4.1.2 Data Ready Pin (DRDY)
        3. 9.4.1.3 Data Retrieval
          1. 9.4.1.3.1 Status Word
          2. 9.4.1.3.2 Readback Length
          3. 9.4.1.3.3 Data Format
        4. 9.4.1.4 Single-Shot Mode
        5. 9.4.1.5 Continuous Conversion Mode
      2. 9.4.2 Multiple-Device Configuration
        1. 9.4.2.1 Cascade Configuration
        2. 9.4.2.2 Daisy-Chain Configuration
    5. 9.5 Programming
      1. 9.5.1 SPI Interface
        1. 9.5.1.1 Chip Select Pin (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
          1. 9.5.1.2.1 SCLK Clocking Methods
        3. 9.5.1.3 Data Input Pin (DIN)
        4. 9.5.1.4 Data Output Pin (DOUT)
      2. 9.5.2 SPI Command Definitions
        1. 9.5.2.1  WAKEUP: Exit Standby Mode
        2. 9.5.2.2  STANDBY: Enter Standby Mode
        3. 9.5.2.3  RESET: Reset Registers to Default Values
        4. 9.5.2.4  START: Start Conversions
        5. 9.5.2.5  STOP: Stop Conversions
        6. 9.5.2.6  RDATAC: Read Data Continuous
        7. 9.5.2.7  SDATAC: Stop Read Data Continuous
        8. 9.5.2.8  RDATA: Read Data
        9. 9.5.2.9  Sending Multibyte Commands
        10. 9.5.2.10 RREG: Read From Register
        11. 9.5.2.11 WREG: Write to Register
    6. 9.6 Register Maps
      1. 9.6.1 Register Descriptions
        1. 9.6.1.1  ID: ID Control Register (address = 00h) (reset = xxh)
        2. 9.6.1.2  CONFIG1: Configuration Register 1 (address = 01h) (reset = 06h)
        3. 9.6.1.3  CONFIG2: Configuration Register 2 (address = 02h) (reset = 40h)
        4. 9.6.1.4  CONFIG3: Configuration Register 3 (address = 03h) (reset = 40h)
        5. 9.6.1.5  LOFF: Lead-Off Control Register (address = 04h) (reset = 00h)
        6. 9.6.1.6  CHnSET: Individual Channel Settings (n = 1 to 8) (address = 05h to 0Ch) (reset = 00h)
        7. 9.6.1.7  RLD_SENSP: RLD Positive Signal Derivation Register (address = 0Dh) (reset = 00h)
        8. 9.6.1.8  RLD_SENSN: RLD Negative Signal Derivation Register (address = 0Eh) (reset = 00h)
        9. 9.6.1.9  LOFF_SENSP: Positive Signal Lead-Off Detection Register (address = 0Fh) (reset = 00h)
        10. 9.6.1.10 LOFF_SENSN: Negative Signal Lead-Off Detection Register (address = 10h) (reset = 00h)
        11. 9.6.1.11 LOFF_FLIP: Lead-Off Flip Register (address = 11h) (reset = 00h)
        12. 9.6.1.12 LOFF_STATP: Lead-Off Positive Signal Status Register (address = 12h) (reset = 00h)
        13. 9.6.1.13 LOFF_STATN: Lead-Off Negative Signal Status Register (address = 13h) (reset = 00h)
        14. 9.6.1.14 GPIO: General-Purpose I/O Register (address = 14h) (reset = 0Fh)
        15. 9.6.1.15 PACE: Pace Detect Register (address = 15h) (reset = 00h)
        16. 9.6.1.16 RESP: Respiration Control Register (address = 16h) (reset = 00h)
        17. 9.6.1.17 CONFIG4: Configuration Register 4 (address = 17h) (reset = 00h)
        18. 9.6.1.18 WCT1: Wilson Central Terminal and Augmented Lead Control Register (address = 18h) (reset = 00h)
        19. 9.6.1.19 WCT2: Wilson Central Terminal Control Register (address = 18h) (reset = 00h)
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Setting the Device for Basic Data Capture
        1. 10.1.1.1 Lead-Off
        2. 10.1.1.2 Right Leg Drive
        3. 10.1.1.3 Pace Detection
      2. 10.1.2 Establishing the Input Common-Mode
      3. 10.1.3 Antialiasing
    2. 10.2 Typical Applications
      1. 10.2.1 ADS129xR Respiration Measurement Using Internal Modulation Circuitry
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Software-Based Artificial Pacemaker Detection Using the PACEOUT Pins on the ADS129x
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power-Up Sequencing
    2. 11.2 Connecting to Unipolar (3 V or 1.8 V) Supplies
    3. 11.3 Connecting to Bipolar (±1.5 V or ±1.8 V) Supplies
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

ZXG Package
64-Pin NFBGA
Top View, Solder Bumps on Bottom Side
ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R po_bga_bas459.gif

Pin Function: NFBGA Package

PIN TYPE DESCRIPTION
NO. NAME
1A IN8P(1) Analog input Differential analog positive input 8 (ADS1298 and ADS1298R)
1B IN7P(1) Analog input Differential analog positive input 7 (ADS1298 and ADS1298R)
1C IN6P(1) Analog input Differential analog positive input 6 (ADS1296, ADS1298, ADS1296R, ADS1298R)
1D IN5P(1) Analog input Differential analog positive input 5 (ADS1296, ADS1298, ADS1296R, ADS1298R)
1E IN4P(1) Analog input Differential analog positive input 4
1F IN3P(1) Analog input Differential analog positive input 3
1G IN2P(1) Analog input Differential analog positive input 2
1H IN1P(1) Analog input Differential analog positive input 1
2A IN8N(1) Analog input Differential analog negative input 8 (ADS1298, ADS1298R)
2B IN7N(1) Analog input Differential analog negative input (ADS1298, ADS1298R)
2C IN6N(1) Analog input Differential analog negative input 6 (ADS1296, ADS1298, ADS1296R, ADS1298R)
2D IN5N(1) Analog input Differential analog negative input 5 (ADS1296, ADS1298, ADS1296R, ADS1298R)
2E IN4N(1) Analog input Differential analog negative input 4
2F IN3N(1) Analog input Differential analog negative input 3
2G IN2N(1) Analog input Differential analog negative input 2
2H IN1N(1) Analog input Differential analog negative input 1
3A RLDIN(1) Analog input Right leg drive input to mux
3B RLDOUT Analog output Right leg drive output
3C RLDINV Analog input/output Right leg drive inverting input
3D WCT Analog output Wilson central terminal output
3E TESTP_PACE_OUT1(1) Analog input/buffer output Internal test signal or single-ended buffer output based on register settings
3F TESTN_PACE_OUT2(1) Analog input/output Internal test signal or single-ended buffer output based on register settings
3G VCAP4 — Analog bypass capacitor; connect 1-μF capacitor to AVSS
3H VREFP Analog input/output Positive reference input/output voltage
4A AVDD Supply Analog supply
4B AVDD Supply Analog supply
4C RLDREF Analog input Right leg drive noninverting input
4D AVSS Supply Analog ground
4E RESV1 Digital input Reserved for future use; must tie to logic low (DGND).
4F RESP_MODN Analog output ADS129xR: modulation clock for respiration measurement, negative side.
ADS129x: leave floating.
4G RESP_MODP Analog output ADS129xR: modulation clock for respiration measurement, positive side.
ADS129x: leave floating.
4H VREFN Analog input Negative reference voltage
5A AVSS Supply Analog ground
5B AVSS Supply Analog ground
5C AVSS Supply Analog ground
5D AVSS Supply Analog ground
5E GPIO4 Digital input/output General-purpose input/output pin 4
5F GPIO1 Digital input/output General-purpose input/output pin 1
5G PWDN Digital input Power-down pin; active low
5H VCAP1 — Analog bypass capacitor; connect 22-μF capacitor to AVSS
6A AVDD Supply Analog supply
6B AVDD Supply Analog supply
6C AVDD Supply Analog supply
6D DRDY Digital output Data ready; active low
6E GPIO3 Digital input/output General purpose input/output pin 3
6F DAISY_IN(2) Digital input Daisy-chain input; if not used, short to DGND.
6G RESET Digital input System-reset pin; active low
6H VCAP2 — Analog bypass capacitor; connect 1-μF capacitor to AVSS
7A AVDD1 Supply Analog supply for charge pump
7B VCAP3 — Analog bypass capacitor; internally generated AVDD + 1.9 V; connect 1-μF capacitor to AVSS
7C DGND Supply Digital ground
7D DGND Supply Digital ground
7E GPIO2 Digital input/output General-purpose input/output pin 2
7F CS Digital input SPI chip select; active low
7G START Digital input Start conversion
7H DGND Supply Digital ground
8A AVSS1 Supply Analog ground for charge pump
8B CLKSEL Digital input Master clock select
8C DVDD Supply Digital power supply
8D DVDD Supply Digital power supply
8E DOUT Digital output SPI data output
8F SCLK Digital input SPI clock
8G CLK Digital input/output External Master clock input or internal clock output.
8H DIN Digital input SPI data input
(1) Connect unused pins to AVDD.
(2) When DAISY_IN is not used, tie to logic 0.
PAG PACKAGE
64-Pin TQFP
Top View
ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R po_qfp_bas459.gif

Pin Functions: TQFP Package

PIN TYPE DESCRIPTION
NO. NAME
1 IN8N(1) Analog input Differential analog negative input 8 (ADS1298)
2 IN8P(1) Analog input Differential analog positive input 8 (ADS1298)
3 IN7N(1) Analog input Differential analog negative input 7 (ADS1298)
4 IN7P(1) Analog input Differential analog positive input 7 (ADS1298)
5 IN6N(1) Analog input Differential analog negative input 6 (ADS1296, ADS1298)
6 IN6P(1) Analog input Differential analog positive input 6 (ADS1296, ADS1298)
7 IN5N(1) Analog input Differential analog negative input 5 (ADS1296, ADS1298)
8 IN5P(1) Analog input Differential analog positive input 5 (ADS1296, ADS1298)
9 IN4N(1) Analog input Differential analog negative input 4
10 IN4P(1) Analog input Differential analog positive input 4
11 IN3N(1) Analog input Differential analog negative input 3
12 IN3P(1) Analog input Differential analog positive input 3
13 IN2N(1) Analog input Differential analog negative input 2
14 IN2P(1) Analog input Differential analog positive input 2
15 IN1N(1) Analog input Differential analog negative input 1
16 IN1P(1) Analog input Differential analog positive input 1
17 TESTP_PACE_OUT1(1) Analog input/buffer output Internal test signal/single-ended buffer output based on register settings
18 TESTN_PACE_OUT2(1) Analog input/output Internal test signal/single-ended buffer output based on register settings
19 AVDD Supply Analog supply
20 AVSS Supply Analog ground
21 AVDD Supply Analog supply
22 AVDD Supply Analog supply
23 AVSS Supply Analog ground
24 VREFP Analog input/output Positive reference input/output voltage
25 VREFN Analog input Negative reference voltage
26 VCAP4 — Analog bypass capacitor; connect 1-μF capacitor to AVSS
27 NC — No connection, can be connected to AVDD or AVSS with a 10-kΩ resistor
28 VCAP1 — Analog bypass capacitor; connect 22-μF capacitor to AVSS
29 NC — No connection, can be connected to AVDD or AVSS with a 10-kΩ resistor
30 VCAP2 — Analog bypass capacitor; connect 1-μF capacitor to AVSS
31 RESV1 Digital input Reserved for future use; must tie to logic low (DGND).
32 AVSS Supply Analog ground
33 DGND Supply Digital ground
34 DIN Digital input SPI data input
35 PWDN Digital input Power-down pin; active low
36 RESET Digital input System-reset pin; active low
37 CLK Digital input/output External Master clock input or internal clock output.
38 START Digital input Start conversion
39 CS Digital input SPI chip select; active low
40 SCLK Digital input SPI clock
41 DAISY_IN(2) Digital input Daisy-chain input; if not used, short to DGND.
42 GPIO1 Digital input/output General-purpose input/output pin 1
43 DOUT Digital output SPI data output
44 GPIO2 Digital input/output General-purpose input/output pin 2
45 GPIO3 Digital input/output General-purpose input/output pin 3
46 GPIO4 Digital input/output General-purpose input/output pin 4
47 DRDY Digital output Data ready; active low
48 DVDD Supply Digital power supply
49 DGND Supply Digital ground
50 DVDD Supply Digital power supply
51 DGND Supply Digital ground
52 CLKSEL Digital input Master clock select
53 AVSS1 Supply Analog ground
54 AVDD1 Supply Analog supply
55 VCAP3 — Analog bypass capacitor; internally generated AVDD + 1.9 V; connect 1-μF capacitor to AVSS
56 AVDD Supply Analog supply
57 AVSS Supply Analog ground
58 AVSS Supply Analog ground
59 AVDD Supply Analog supply
60 RLDREF Analog input Right leg drive noninverting input
61 RLDINV Analog input/output Right leg drive inverting input
62 RLDIN(1) Analog input Right leg drive input to mux
63 RLDOUT Analog output Right leg drive output
64 WCT Analog output Wilson Central Terminal output
(1) Connect unused pins to AVDD.
(2) When DAISY_IN is not used, tie to logic 0.