SBAS717A June   2015  – June 2015 ADS58J63

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  AC Performance
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Typical Characteristics: 14-Bit Burst Mode
    10. 6.10 Typical Characteristics: Mode 2
    11. 6.11 Typical Characteristics: Mode 0
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Recommended Input Circuitry
    4. 7.4 Device Functional Modes
      1. 7.4.1  Digital Features
      2. 7.4.2  Mode 0 - Decimation by 2 with IQ Outputs for up to 220 MHz of IQ Bandwidth
      3. 7.4.3  Mode 2 - Decimation by 2 for up to 110 MHz of Real Bandwidth
      4. 7.4.4  Mode 4/7 - Decimation by 2 with Real Outputs for up to 110 MHz of Bandwidth
      5. 7.4.5  Mode 5 - Decimation by 2 with IQ Outputs for up to 110 MHz of IQ Bandwidth
      6. 7.4.6  Mode 6 - Decimation by 4 with IQ Outputs for up to 110 MHz of IQ Bandwidth
      7. 7.4.7  Mode 8 - Burst Mode
      8. 7.4.8  Trigger Input
      9. 7.4.9  Manual Trigger Mode
      10. 7.4.10 Auto Trigger Mode
      11. 7.4.11 Over-range Indication
      12. 7.4.12 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 Device Configuration
        1. 7.5.1.1  Details of Serial Interface
        2. 7.5.1.2  Serial Register Write: Analog Bank
        3. 7.5.1.3  Serial Register Readout: Analog Bank
        4. 7.5.1.4  JESD Bank SPI Page Selection
        5. 7.5.1.5  Serial Register Write: Analog Bank
        6. 7.5.1.6  Serial Register Readout: Analog Bank
        7. 7.5.1.7  Digital Bank SPI Page Selection
        8. 7.5.1.8  Serial Register Write - Digital Bank
        9. 7.5.1.9  Individual Channel Programming
        10. 7.5.1.10 Serial Register Readout - Digital Bank
      2. 7.5.2 JESD204B Interface
        1. 7.5.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 7.5.2.2 JESD204B Frame Assembly
        3. 7.5.2.3 JESD Output Switch
          1. 7.5.2.3.1 Serdes Transmitter Interface
          2. 7.5.2.3.2 SYNCb Interface
          3. 7.5.2.3.3 Eye Diagram
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Info
      2. 7.6.2 Example Register Writes
      3. 7.6.3 Register Descriptions
        1. 7.6.3.1  Register 0h (offset = 0h) [reset = 0h]
        2. 7.6.3.2  Register 3h/4h (offset = 3h/4h) [reset = 0h]
        3. 7.6.3.3  Register 5h (offset = 5h) [reset = 0h]
        4. 7.6.3.4  Register 11h (offset = 11h) [reset = 0h]
        5. 7.6.3.5  Master Page (80h)
          1. 7.6.3.5.1  Register 20h (address = 20h) [reset = 0h] , Master Page (080h)
          2. 7.6.3.5.2  Register 21h (address = 21h) [reset = 0h] , Master Page (080h)
          3. 7.6.3.5.3  Register 23h (address = 23h), Master Page (080h)
          4. 7.6.3.5.4  Register 24h (address = 24h) [reset = 0h] , Master Page (080h)
          5. 7.6.3.5.5  Register 26h (address = 26h), Master Page (080h)
          6. 7.6.3.5.6  Register 3Ah (address = 3Ah) [reset = 0h] , Master Page (80h)
          7. 7.6.3.5.7  Register 39h (address = 39h) [reset = 0h] , Master Page (80h)
          8. 7.6.3.5.8  Register 53h (address = 53h) [reset = 0h] , Master Page (80h)
          9. 7.6.3.5.9  Register 55h (address = 55h) [reset = 0h] , Master Page (80h)
          10. 7.6.3.5.10 Register 56h (address = 56h) [reset = 0h] , Master Page (80h)
          11. 7.6.3.5.11 Register 59h (address = 59h) [reset = 0h] , Master Page (80h)
        6. 7.6.3.6  ADC Page (0Fh)
          1. 7.6.3.6.1 Register 5Fh (address = 5Fh) [reset = 0h] , ADC Page (0Fh)
          2. 7.6.3.6.2 Register 60h (address = 60h) [reset = 0h] , ADC Page (0Fh)
          3. 7.6.3.6.3 Register 60h (address = 61h) [reset = 0h], ADC Page (0Fh)
          4. 7.6.3.6.4 Register 6Ch (address = 6Ch) [reset = 0h], ADC Page (0Fh)
          5. 7.6.3.6.5 Register 6Dh (address = 6Dh) [reset = 0h], ADC Page (0Fh)
          6. 7.6.3.6.6 Register 74h(address = 74h) [reset = 0h], ADC Page (0Fh)
          7. 7.6.3.6.7 Register 75h/76h/77h/78h (address = 75h/76h/77h/78h) [reset = 0h], ADC Page (0Fh)
        7. 7.6.3.7  Interleaving Engine Page (6100h)
          1. 7.6.3.7.1 Register 18h (address = 18h) [reset = 0h], Interleaving Engine Page (6100h)
          2. 7.6.3.7.2 Register 68h (address = 68h) [reset = 0h], Interleaving Engine Page (6100h)
        8. 7.6.3.8  Decimation Filter Page (6141h) Registers
          1. 7.6.3.8.1 Register 0h (address = 0h) [reset = 0h]
          2. 7.6.3.8.2 Register 1h (address = 1h) [reset = 0h]
          3. 7.6.3.8.3 Register 2h (address = 2h) [reset = 0h]
        9. 7.6.3.9  Main Digital Page (6800h) Registers
          1. 7.6.3.9.1 Register 0h (address = 0h) [reset = 0h], Main Digital Page (6800h)
          2. 7.6.3.9.2 Register 42h(address = 42h) [reset = 0h], Main Digital Page (6800h)
          3. 7.6.3.9.3 Register 4Eh (address = 4Eh) [reset = 0h], Main Digital Page (6800h)
          4. 7.6.3.9.4 Register ABh (address = ABh) [reset = 0h], Main Digital Page (6800h)
          5. 7.6.3.9.5 Register ADh (address = ADh) [reset = 0h], Main Digital Page (6800h)
          6. 7.6.3.9.6 Register F7h (address = F7h) [reset = 0h], Main Digital Page (68h)
        10. 7.6.3.10 JESD Digital Page (6900h) Registers
          1. 7.6.3.10.1 Register 0h (address = 0h) [reset = 0h], JESD Digital Page (6900h)
          2. 7.6.3.10.2 Register 1h (address = 1h) [reset = 0h], JESD Digital Page (6900h)
          3. 7.6.3.10.3 Register 2h (address = 2h) [reset = 0h], JESD Digital Page (6900h)
          4. 7.6.3.10.4 Register 3h (address = 3h) [reset = 0h], JESD Digital Page (6900h)
          5. 7.6.3.10.5 Register 5h (address = 5h) [reset = 0h], JESD Digital Page (6900h)
          6. 7.6.3.10.6 Register 6h (address = 6h) [reset = 0h], JESD Digital Page (6900h)
          7. 7.6.3.10.7 Register 17h (address = 17h) [reset = 0h], JESD Digital Page (6900h)
          8. 7.6.3.10.8 Register 19h/1Ah/1Bh/1Ch (address = 19h/1Ah/1Bh/1Ch) [reset = 0h], JESD Digital Page (6900h)
            1. 7.6.3.10.8.1 Register 1Dh/1Eh/1Fh/20h (address = 1Dh/1Eh/1Fh/20h) [reset = 0h], JESD Digital Page (6900h)
            2. 7.6.3.10.8.2 Register 21h (address = 21h) [reset = 0h], JESD Digital Page (6900h)
            3. 7.6.3.10.8.3 Register 22h (address = 22h) [reset = 0h], JESD Digital Page (6900h)
        11. 7.6.3.11 JESD Analog Page (6A00h) Register
          1. 7.6.3.11.1 Register 12h/13h (address 12h/13h) [reset = 0h], JESD Analog Page (6Ah)
          2. 7.6.3.11.2 16h (address = 16h) [reset = 0h], JESD Analog Page (6A00h)
          3. 7.6.3.11.3 Register 1Bh (address = 1Bh) [reset = 0h], JESD Analog Page (6Ah)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Start-Up Sequence
      2. 8.1.2 Hardware Reset
      3. 8.1.3 SNR and Clock Jitter
      4. 8.1.4 ADC Test Pattern
        1. 8.1.4.1 ADC Section
        2. 8.1.4.2 Transport Layer Pattern
        3. 8.1.4.3 Link Layer Pattern
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Quad Channel
  • 14-Bit Resolution
  • Maximum Clock Rate: 500 MSPS
  • Input Bandwidth (3 dB): 900 MHz
  • On-Chip Dither
  • Analog Input Buffer with High-Impedance Input
  • Output Options:
    • Rx: Decimate-by-2 and -4 Options with Low-Pass Filter
    • 200-MHz Complex Bandwidth or 100-MHz Real Bandwidth Support
    • DPD FB: Burst Mode with 14-Bit Output
  • 1.9-VPP Differential Full-Scale Input
  • JESD204B Interface:
    • Subclass 1 Support
    • 1 Lane per ADC Up to 10 Gbps
    • Dedicated SYNC pin for pair of channels
  • Support for Multi-Chip Synchronization
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • Key Specifications:
    • Power Dissipation: 675 mW/ch
    • Spectral Performance (Un-decimated)
      • fIN = 190 MHz IF at –1 dBFS:
        • SNR: 70.4 dBFS
        • NSD: –154.4 dBFS/Hz
        • SFDR: 86 dBc (HD2, HD3),
          95 dBFS (non HD2, HD3)
      • fIN = 370 MHz IF at –3 dBFS:
        • SNR: 68.5 dBFS
        • NSD: –152.5 dBFS/Hz
        • SFDR: 81 dBc (HD2, HD3),
          86 dBFS (non HD2, HD3)

2 Applications

  • Multi-Carrier GSM Cellular Infrastructure Base Stations
  • Multi-Carrier Multi-Mode Cellular Infrastructure Base Stations
  • Telecommunications Receiver
  • Telecom DPD Observation Receiver

3 Description

The ADS58J63 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS58J63 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS58J63 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth. The ADS58J63 also supports a 14-bit, 500-MSPS output in burst-mode making the device suitable for a DPD observation receiver.

The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
ADS58J63 VQFN (72) 10.00 mm x 10.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Block Diagram

ADS58J63 bd_bas717.gif

4 Revision History

Changes from * Revision (June 2015) to A Revision

  • Changed From Product Preview To Production datasheet Go