Product details


Number of input channels 4 Resolution (Bits) 14 Sample rate (Max) (MSPS) 500 Features Decimating Filter, Differential Inputs, High Dynamic Range, Nap Mode, Out of Range Indicator, Power Down Analog input BW (MHz) 900 SFDR (Typ) (dB) 89 SNR (Typ) (dB) 70.8 Power consumption (Typ) (mW) 2700 Logic voltage DV/DD (Max) (V) 2 Logic voltage DV/DD (Min) (V) 1.8 Analog voltage AVDD (Max) (V) 2 Analog voltage AVDD (Min) (V) 1.8 Operating temperature range (C) -40 to 85 open-in-new Find other Receivers

Package | Pins | Size

VQFNP (RMP) 72 100 mm² 10 x 10 open-in-new Find other Receivers


  • Quad Channel
  • 14-Bit Resolution
  • Maximum Clock Rate: 500 MSPS
  • Input Bandwidth (3 dB): 900 MHz
  • On-Chip Dither
  • Analog Input Buffer with High-Impedance Input
  • Output Options:
    • Rx: Decimate-by-2 and -4 Options with Low-
      Pass Filter
    • 200-MHz Complex Bandwidth or 100-MHz
      Real Bandwidth Support
    • DPD FB: Burst Mode with 14-Bit Output
  • 1.9-VPP Differential Full-Scale Input
  • JESD204B Interface:
    • Subclass 1 Support
    • 1 Lane per ADC Up to 10 Gbps
    • Dedicated SYNC pin for pair of channels
  • Support for Multi-Chip Synchronization
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • Key Specifications:
    • Power Dissipation: 675 mW/ch
    • Spectral Performance (Un-decimated)
      • fIN = 190 MHz IF at –1 dBFS:
        • SNR: 70.4 dBFS
        • NSD: –154.4 dBFS/Hz
        • SFDR: 86 dBc (HD2, HD3),
          95 dBFS (non HD2, HD3)
      • fIN = 370 MHz IF at –3 dBFS:
        • SNR: 68.5 dBFS
        • NSD: –152.5 dBFS/Hz
        • SFDR: 81 dBc (HD2, HD3),
          86 dBFS (non HD2, HD3)
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The ADS58J63 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS58J63 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS58J63 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth. The ADS58J63 also supports a 14-bit, 500-MSPS output in burst-mode making the device suitable for a DPD observation receiver.

The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.

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Technical documentation

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Type Title Date
* Data sheet ADS58J63 Quad-Channel, 14-Bit, 500-MSPS Telecom Receiver Device datasheet (Rev. A) Jun. 29, 2015
Technical article Why should you care about the noise immunity of MLVDS drivers and receivers? Jul. 26, 2017
Technical article How to minimize filter loss when you drive an ADC Oct. 20, 2016
Technical article RF sampling: analog-to-digital converter linearity sets sensitivity Sep. 29, 2016
Technical article RF sampling: linearity performance is not so straightforward Aug. 30, 2016
User guide ADS54J/58J6x Evaluation Module User's Guide (Rev. D) Jan. 13, 2016
User guide ADS58J63_A_DESIGN_PACKAGE Jun. 17, 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The ADS58J63EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS58J63 and LMK04828 clock jitter cleaner. The ADS58J63 is a low power, wide bandwidth, 14-bit, 500-MSPS quad analog to digital converter (ADC) with a buffered analog input and outputs featuring (...)

  • Flexible transformer coupled analog input to allow for a variety of sources and frequencies
  • Easy to use software GUI to configure the ADS58J63 and LMK04828 for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High Speed Data Converter Pro software
  • Simple (...)

Software development

High-speed data converter pro software
DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
  • Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
  • Works with all TI high-speed DAC, ADC, and AFE products
  • Provides time-domain and frequency-domain analysis
  • Supports single-tone, multi-tone, and modulated (...)

Design tools & simulation

SBAM251.ZIP (46 KB) - IBIS Model
SBAM325.ZIP (5519 KB) - IBIS-AMI Model
SBAC155A.ZIP (3977 KB)

CAD/CAE symbols

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VQFN (RMP) 72 View options

Ordering & quality

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