SBAS584B October   2013  – August 2014 ADS7253 , ADS7853 , ADS8353

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configurations and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Handling Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS8353
    6. 7.6  Electrical Characteristics: ADS7853
    7. 7.7  Electrical Characteristics: ADS7253
    8. 7.8  Electrical Characteristics: All Devices
    9. 7.9  Timing Requirements: Interface Mode
    10. 7.10 Timing Characteristics: Serial Interface
    11. 7.11 Typical Characteristics: ADS8353
    12. 7.12 Typical Characteristics: ADS7853
    13. 7.13 Typical Characteristics: ADS7253
    14. 7.14 Typical Characteristics: Common to ADS8353, ADS7853, and ADS7253
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference
      2. 8.3.2 Analog Inputs
        1. 8.3.2.1 Analog Input: Full-Scale Range Selection
        2. 8.3.2.2 Analog Input: Single-Ended and Pseudo-Differential Configurations
      3. 8.3.3 Transfer Function
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps and Serial Interface
      1. 8.5.1 Serial Interface
      2. 8.5.2 Write to User Programmable Registers
        1. 8.5.2.1 Configuration Register (CFR)
        2. 8.5.2.2 REFDAC Registers (REFDAC_A and REFDAC_B)
      3. 8.5.3 Data Read Operation
        1. 8.5.3.1 Reading User-Programmable Registers
        2. 8.5.3.2 Conversion Data Read
          1. 8.5.3.2.1 32-CLK, Dual-SDO Mode (CFR.B11 = 0, CFR.B10 = 0, Default)
          2. 8.5.3.2.2 32-CLK, Single-SDO Mode (CFR.B11 = 0, CFR.B10 = 1)
          3. 8.5.3.2.3 16-CLK, Dual-SDO Mode (CFR.B11 = 1, CFR.B10 = 0)
          4. 8.5.3.2.4 16-CLK, Single-SDO Mode (CFR.B11 = 1, CFR.B10 = 1)
      4. 8.5.4 Low-Power Modes
        1. 8.5.4.1 STANDBY Mode
        2. 8.5.4.2 Software Power-Down (SPD) Mode
      5. 8.5.5 Frame Abort, Reconversion, or Short-Cycling
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Amplifier Selection
      2. 9.1.2 Antialiasing Filter
    2. 9.2 Typical Applications
      1. 9.2.1 DAQ Circuit to Achieve Maximum SINAD for a 10-kHz Input Signal at Full Throughput
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 DAQ Circuit to Achieve Maximum SINAD for a 100-kHz Input Signal at Full Throughput
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power-Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Related Documentation
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Figure 117 shows a board layout example for the ADS8353, ADS7853, and ADS7253 with the WQFN package. Use a ground plane underneath the device and partition the PCB into analog and digital sections. Avoid crossing digital lines with the analog signal path and keep the analog input signals and the reference input signals away from noise sources. As shown in Figure 117, the analog input and reference signals are routed on the left side of the board and the digital connections are routed on the right side of the device.

The power sources to the device must be clean and well-bypassed. Use 10-μF, ceramic bypass capacitors in close proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors. Connect all ground pins to the ground plane using short, low impedance paths.

The REFIO-A and REFIO-B reference inputs and outputs are bypassed with 10-μF, X7R-grade, 0805-size, 16-V rated ceramic capacitors (CREF-x). Place the reference bypass capacitors as close as possible to the reference REFIO-x pins and connect the bypass capacitors using short, low-inductance connections. Avoid placing vias between the REFIO-x pins and the bypass capacitors. Small 0.1-Ω to 0.2-Ω resistors (RREF-x) are used in series with the reference bypass capacitors to improve stability.

The fly-wheel RC filters are placed immediately next to the input pins. Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes. Figure 117 shows CIN-A and CIN-B filter capacitors placed across the analog input pins of the device.

11.2 Layout Example

LAYOUT.gifFigure 117. Recommended Layout