SBAS404D October   2006  – February 2016 ADS8556 , ADS8557 , ADS8558

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: General
    6. 6.6  Electrical Characteristics: ADS8556
    7. 6.7  Electrical Characteristics: ADS8557
    8. 6.8  Electrical Characteristics: ADS8558
    9. 6.9  Power Dissipation Characteristics
    10. 6.10 Serial Interface Timing Requirements
    11. 6.11 Parallel Interface Timing Requirements (Read Access)
    12. 6.12 Parallel Interface Timing Requirements (Write Access)
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog
        1. 7.3.1.1 Analog Inputs
        2. 7.3.1.2 Analog-to-Digital Converter (ADC)
        3. 7.3.1.3 Conversion Clock
        4. 7.3.1.4 CONVST_x
        5. 7.3.1.5 BUSY/INT
        6. 7.3.1.6 Reference
      2. 7.3.2 Digital
        1. 7.3.2.1 Device Configuration
        2. 7.3.2.2 Parallel Interface
        3. 7.3.2.3 Serial Interface
        4. 7.3.2.4 Output Data Format
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hardware Mode
      2. 7.4.2 Software Mode
      3. 7.4.3 Daisy-Chain Mode (in Serial Mode Only)
      4. 7.4.4 Sequential Mode (in Software Mode with External Conversion Clock Only)
      5. 7.4.5 Reset and Power-Down Modes
    5. 7.5 Register Maps
      1. 7.5.1 Control Register (CR); Default Value = 0x000003FF
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The ADS855x series includes six 16-, 14-, and 12-bit analog-to-digital converters (ADCs) respectively that operate based on the successive approximation register (SAR) principle. The architecture is designed on the charge redistribution principle that inherently includes a sample-and-hold function. The six analog inputs are grouped into three channel pairs. These channel pairs can be sampled and converted simultaneously, preserving the relative phase information of the signals of each pair. Separate conversion start signals allow simultaneous sampling on each channel pair: on four channels or on all six channels.

These devices accept single-ended, bipolar analog input signals in the selectable ranges of ±4 VREF or ±2 VREF with an absolute value of up to ±12 V; see the Analog Inputs section.

The devices offer an internal 2.5-V or 3-V reference source followed by a 10-bit, digital-to-analog converter (DAC) that allows the reference voltage VREF to be adjusted in 2.44-mV or 2.93-mV steps, respectively.

The ADS855x also offers a selectable parallel or serial interface that can be used in hardware or software mode; see the Device Configuration section for details.

7.2 Functional Block Diagram

ADS8556 ADS8557 ADS8558 pg1_fbd_bas531.gif

7.3 Feature Description

7.3.1 Analog

This section addresses the analog input circuit, the ADCs and control signals, and the reference design of the device.

7.3.1.1 Analog Inputs

The inputs and the converters are of single-ended, bipolar type. The absolute voltage range can be selected using the RANGE pin (in hardware mode) or RANGE_x bits (in software mode) in the control register (CR) to either ±4 VREF or ±2 VREF. With the reference set to 2.5 V (CR bit C18 = 0), the input voltage range can be ±10 V or ±5 V. With the reference source set to 3 V (CR bit C18 = 1), an input voltage range of ±12 V or ±6 V can be configured. The logic state of the RANGE pin is latched with the falling edge of BUSY (if CR bit C20 = 0).

The input current on the analog inputs depends on the actual sample rate, input voltage, and signal source impedance. Essentially, the current into the analog inputs charges the internal capacitor array only during the sampling period (tACQ). The source of the analog input voltage must be able to charge the input capacitance of 10 pF in ±4-VREF mode or 20 pF in ±2-VREF to a 12-, 14-, 16-bit accuracy level within the acquisition time of 280 ns at maximum data rate; see Figure 1. During the conversion period, there is no further input current flow and the input impedance is greater than 1 MΩ. To ensure a defined start condition, the sampling capacitors of the ADS855x are pre-charged to a fixed internal voltage before switching into sampling mode.

To maintain the linearity of the converter, the inputs must always remain within the specified range of HVSS – 0.2 V to HVDD + 0.2 V.

The minimum –3-dB bandwidth of the driving operational amplifier can be calculated using Equation 1:

Equation 1. ADS8556 ADS8557 ADS8558 q_f3db_tacq_bas404.gif

where

  • n = 16, 14, or 12; n is the resolution of the ADS855x

With a minimum acquisition time of tACQ = 280 ns, the required minimum bandwidth of the driving amplifier is 6.7 MHz for the ADS8556, 6 MHz for the ADS8557, or 5.2 MHz for the ADS8558. The required bandwidth can be lower if the application allows a longer acquisition time. A gain error occurs if a given application does not fulfill the bandwidth requirement shown in Equation 1.

A driving operational amplifier may not be required if the impedance of the signal source (RSOURCE) fulfills the requirement of Equation 2:

Equation 2. ADS8556 ADS8557 ADS8558 q_rsource_bas404.gif

where

  • n = 16, 14, or 12; n is the resolution of the ADC
  • CS = 10 pF is the sample capacitor value for VIN = ±4 × VREF mode
  • RSER = 200 Ω is the input resistor value
  • RSW = 130 Ω is the switch resistance value

With tACQ = 280 ns, the maximum source impedance must be less than 2.0 kΩ for the ADS8556, 2.3 kΩ for the ADS8557, and 2.7 kΩ for the ADS8558 in VIN = ±4 VREF mode or less than 0.8 kΩ for the ADS8556, 1.0 kΩ for the ADS8557, and 1.2 kΩ for the ADS8558 in VIN = ±2 VREF mode. The source impedance can be higher if the application allows longer acquisition time.

7.3.1.2 Analog-to-Digital Converter (ADC)

The devices include six ADCs that operate with either an internal or an external conversion clock. The conversion time can be as low as 1.09 μs with an internal conversion clock (ADS8558). When an external clock and reference are used, the minimum conversion time is 925 ns.

7.3.1.3 Conversion Clock

The device uses either an internally-generated or an external (XCLK) conversion clock signal (in software mode only). In default mode, the device generates an internal clock. When the CLKSEL bit is set high (bit C11 in the CR), an external conversion clock of up to 20 MHz (max) can be applied on pin 27. In both cases, 18.5 clock cycles are required for a complete conversion including the pre-charging of the sample capacitors. The external clock can remain low between conversions.

The conversion clock duty cycle must be 50%. However, the ADS855x functions properly with a duty cycle between 45% and 55%.

7.3.1.4 CONVST_x

The analog inputs of each channel pair (CH_x0, CH_x1) are held with the rising edge of the corresponding CONVST_x signal. Only in software mode (except for sequential mode) is CONVST_A used for all six ADCs. The conversion automatically starts with the next edge of the conversion clock. CONVST_x must remain high during the entire conversion cycle and the BUSY signal must remain active. A falling edge during an ongoing conversion puts the related ADC pair into partial power-down mode, see the Reset and Power-Down Modes section for more details.

For simultaneous sampling, connecting all associated CONVST_x pins together is recommended. If the CONVST_x signals are not tied together, a maximum skew of 4 ns must be ensured for all three signals in any order. A CONVST_x signal issued during an ongoing conversion on any channel is blocked, except in sequential mode; see the Sequential Mode section for more details.

If a parallel interface is used, the behavior of the output port depends on which CONVST_x signals are issued. Figure 36 shows examples of different scenarios.

ADS8556 ADS8557 ADS8558 ai_tim_dout-convst_x_bas404.gif

NOTE:

Boxed areas indicate the minimum required frame to acquire all data.
Figure 36. Data Output versus CONVST_x

7.3.1.5 BUSY/INT

The BUSY signal indicates if a conversion is in progress. The BUSY signal goes high with a rising edge of any CONVST_x signal and goes low when the output data of the last channel pair are available in the respective output register. The readout of the data can be initiated immediately after the falling edge of BUSY. A falling edge of a CONVST_x input during an ongoing conversion (when BUSY is high) powers down the corresponding ADC pair.

In sequential mode, the BUSY signal goes low only for one clock cycle; see the Sequential Mode section for more details.

The polarity of the BUSY/INT signal can be changed using CR bit C20.

7.3.1.6 Reference

The ADS855x provides an internal, low-drift, 2.5-V reference source. To increase the input voltage range, the reference voltage can be switched to 3-V mode using the VREF bit (bit C18 in the CR). The reference feeds a 10-bit string-DAC controlled by bits C[9:0] in the control register. The buffered DAC output is connected to the REFIO pin. In this way, the voltage at this pin is programmable in 2.44-mV (2.92 mV in 3-V mode) steps and adjustable to the application needs without additional external components. The actual output voltage can be calculated using Equation 3:

Equation 3. ADS8556 ADS8557 ADS8558 q_vref_bas404.gif

where

  • Range = the chosen maximum reference voltage output range (2.5 V or 3 V)
  • Code = the decimal value of the DAC register content

Table 1 lists some examples of internal reference DAC settings with a reference range set to 2.5 V. However, to ensure proper performance, the DAC output voltage must not be programmed below 0.5 V.

Decouple the buffered output of the DAC with a 100-nF capacitor (minimum); for best performance, a 470-nF capacitor is recommended. If the internal reference is placed into power-down (default), an external reference voltage can drive the REFIO pin.

The voltage at the REFIO pin is buffered with three internal amplifiers, one for each ADC pair. The output of each buffer must be decoupled with a 10-μF capacitor between pin pairs 53 and 54, 55 and 56, and 57 and 58. The 10-μF capacitors are available as ceramic 0805-SMD components and in X5R quality.

The internal reference buffers can be powered down to decrease the power dissipation of the device. In this case, external reference drivers can be connected to REFC_A, REFC_B, and REFC_C pins. With 10-μF decoupling capacitors, the minimum required bandwidth can be calculated using Equation 4:

Equation 4. ADS8556 ADS8557 ADS8558 q_f3db_tconv_bas404.gif

With the minimum tCONV of 1.09 μs, the external reference buffers require a minimum bandwidth of 102 kHz.

Table 1. DAC Setting Examples (2.5-V Operation)

VREF OUT (V) DECIMAL CODE BINARY CODE HEXADECIMAL CODE
0.500 204 00 1100 1100 CC
1.25 511 01 1111 1111 1FF
2.500 1023 11 1111 1111 3FF

7.3.2 Digital

This section describes the digital control and the timing of the device in detail.

7.3.2.1 Device Configuration

Depending on the desired mode of operation, the ADS855x can be configured using the external pins or the control register (CR), as shown in Table 2.

Table 2. ADS855x Configuration Settings

INTERFACE MODE HARDWARE MODE (HW/SW = 0)
CONVERSION START CONTROLLED BY SEPARATE CONVST_x PINS		 SOFTWARE MODE (HW/SW = 1)
CONVERSION START CONTROLLED BY CONVST_A PIN ONLY, EXCEPT IN SEQUENTIAL MODE
Parallel
(PAR/SER = 0)		 Configuration using pins, optionally, control bits C[22:18], C[15:13], and C[9:0] Configuration using control register bits C[31:0] only;
status of pins 27 (only if used as RANGE input) and 63 is disregarded
Serial
(PAR/SER = 1)		 Configuration using pins, optionally, control bits C[22:18], C[15:13], and C[9:0]; bits C[31:24] are disregarded Configuration using control register bits C[31:0] only; status of pins 1, 27 (only if used as RANGE input), and 63 is disregarded; each access requires a control register update via SDI (see the Serial Interface section for details)

7.3.2.2 Parallel Interface

To use the device with the parallel interface, hold the PAR/SER pin low. The maximum achievable data throughput rate using the internal clock is 630 kSPS for the ADS8556, 670 kSPS for the ADS8557, and 730 kSPS for the ADS8558 in this case.

Access to the ADS855x is controlled as illustrated in Figure 3 and Figure 4.

The device can either operate with a 16-bit (WORD/BYTE pin set low) or an 8-bit (WORD/BYTE pin set high) parallel interface. If 8-bit operation is used, the HBEN pin selects if the low-byte (DB7 low) or the high-byte (DB7 high) is available on the data output DB[15:8] first.

7.3.2.3 Serial Interface

The serial interface mode is selected by setting the PAR/SER pin high. In this case, each data transfer starts with the falling edge of the frame synchronization input (FS). The conversion results are presented on the serial data output pins SDO_A, SDO_B, and SDO_C depending on the selections made using the SEL_x pins. Starting with the most significant bit (MSB), the output data are changed at the rising edge of SCLK so that the host processor can read it at the following falling edge. Output data of the ADS8557 and ADS8558 maintain the 16-bit format with leading zeros.

Serial data input SDI are latched at the falling edge of SCLK.

The serial interface can be used with one, two, or three output ports. These ports are enabled with pins SEL_A, SEL_B, and SEL_C. If all three serial data output ports (SDO_A, SDO_B, and SDO_C) are selected, the data can be read with either two 16-bit data transfers or with one 32-bit data transfer. The data of channels CH_x0 are available first, followed by data from channels CH_x1. The maximum achievable data throughput rate is 450 kSPS for the ADS8556, 470 kSPS for the ADS8557, and 500 kSPS for the ADS8558 in this case.

If the application allows a data transfer using two ports only, then the SDO_A and SDO_B outputs are used. The device outputs data from channel CH_A0 followed by CH_A1 and CH_C0 on SDO_A and data from channel CH_B0 followed by CH_B1 and CH_C1 occurs on SDO_B. In this case, a data transfer of three consecutive 16-bit words or one continuous 48-bit word is supported. The maximum achievable data throughput rate is 375 kSPS for the ADS8556, 390 kSPS for the ADS8557, and 400 kSPS for the ADS8558.

The output SDO_A is selected if only one serial data port is used in the application. Data are available in the following order: CH_A0, CH_A1, CH_B0, CH_B1, CH_C0, and, finally CH_C1. Data can be read using six 16-bit transfers, three 32-bit transfers, or a single 96-bit transfer. The maximum achievable data throughput rate is 250 kSPS for the ADS8556, ADS8557 and 260 kSPS for the ADS8558 in this case.

Figure 2 (the serial operation timing diagram) and Figure 37 illustrate all possible scenarios in more detail.

ADS8556 ADS8557 ADS8558 ai_tim_ser_iface_2sdo_bas404.gif Figure 37. Serial Interface: Data Output with One or Two Active SDOs

7.3.2.4 Output Data Format

The data output format of the ADS855x is binary twos complement, as shown in Table 3.

For the ADS8557, which delivers 14-bit conversion results, the leading two bits of the 16-bit frame are '0' in the serial interface mode. In parallel interface mode, the output pins DB[15:14] are held low.

Respectively, when the ADS8558 outputs 12 bits of data, the first four bits of a serial 16-bit frame are zeros, in parallel interface mode the output pins DB[15:12] are held low.

Table 3. Output Data Format

DESCRIPTION INPUT VOLTAGE VALUE BINARY CODE (HEXADECIMAL CODE)
ADS8556 ADS8557 ADS8558
Positive full-scale 4 VREF or 2 VREF 0111 1111 1111 1111 (7FFF) 0001 1111 1111 1111 (1FFF) 0000 0111 1111 1111 (7FF)
Midscale + 0.5LSB VREF / (2 × resolution) 0000 0000 0000 0000 (0000) 0000 0000 0000 0000 (0000) 0000 0000 0000 0000 (0000)
Midscale – 0.5LSB –VREF / (2 × resolution) 1111 1111 1111 1111 (FFFF) 0011 1111 1111 1111 (3FFF) 0000 1111 1111 1111 (FFF)
Negative full-scale –4 VREF or –2 VREF 1000 0000 0000 0000 (8000) 0010 0000 0000 0000 (2000) 0000 1000 0000 0000 (800)

7.4 Device Functional Modes

7.4.1 Hardware Mode

With the HW/SW input (pin 62) set low, the device functions are controlled via the pins and, optionally, control register bits C[22:18], C[15:13], and C[9:0].

Generally, the device can be used in hardware mode and switched into software mode to initialize or adjust the control register settings (for example, the internal reference DAC) and switched back to hardware mode thereafter.

7.4.2 Software Mode

When the HW/SW input is set high, the device operates in software mode with functionality set only by the control register bits (corresponding pin settings are ignored).

If the parallel interface is used, an update of all control register settings is performed by issuing two 16-bit write accesses on pins DB[15:0] in word mode or four 8-bit accesses on pins DB[15:8] in byte mode (to avoid losing data, the entire sequence must be finished before starting a new conversion). Hold CS low during the two or four write accesses to completely update the configuration register. Updating only the upper eight bits (C[31:24]) is also possible using a single write access and pins DB[15:8] in both word and byte modes. In word mode, the first write access updates only the upper eight bits and stores the lower eight bits (C[23:16]) for an update that takes place with the second write access along with C[15:0].

If the serial interface is used, input data containing control register contents are required with each read access to the device in this mode (combined read/write access). For initialization purposes, all 32 bits of the register must be set (bit C16 must be set to '1' during that access to allow the update of the entire register content). To minimize switching noise on the interface, an update of the first eight bits (C[31:24]) with the remaining bits held low can be performed thereafter.

Figure 42 illustrates the different control register update options.

7.4.3 Daisy-Chain Mode (in Serial Mode Only)

The serial interface of the ADS855x supports a daisy-chain feature that allows cascading of multiple devices to minimize the board space requirements and simplify routing of the data and control lines. In this case, pins DB5/DCIN_A, DB4/DCIN_B, and DB3/DCIN_C are used as serial data inputs for channels A, B, and C, respectively. Figure 38 shows an example of a daisy-chain connection of three devices sharing a common CONVST line to allow simultaneous sampling of 18 analog channels along with the corresponding timing diagram. To activate the daisy-chain mode, the DCEN pin must be pulled high. As a result of the time specifications tS1, tH1, and tD3, the maximum SCLK frequency that can be used in daisy-chain mode is 27.78 MHz (assuming a 50% duty cycle).

ADS8556 ADS8557 ADS8558 ai_daisy-chain_bas404.gif Figure 38. Example of Daisy-Chaining Three ADS8556s

7.4.4 Sequential Mode (in Software Mode with External Conversion Clock Only)

The three channel pairs of the ADS855x can be run in sequential mode, with the corresponding CONVST_x signals interleaved, when an external clock is used. To activate the device in sequential mode, CR bits C11 (CLKSEL) and C23 (SEQ) must be asserted. In this case, the BUSY output indicates a finished conversion by going low (when C20 = 0) or high (when C20 = 1) for only a single conversion clock cycle in case of ongoing conversions of any other channel pairs. Figure 39 shows the behavior of the BUSY output in this mode. Initiate each conversion start during the high phase of the external clock, as shown in Figure 39. The minimum time required between two CONVST_x pulses is the time required to read the conversion result of a channel (pair).

ADS8556 ADS8557 ADS8558 ai_tim_seq_mode_bas404.gif
1. EOC = end of conversion (internal signal).
Figure 39. Sequential Mode Timing

7.4.5 Reset and Power-Down Modes

The device supports two reset mechanisms: a power-on reset (POR) and a pin-controlled reset (RESET) that can be issued using pin 28. Both the POR and RESET act as a master reset that causes any ongoing conversion to be interrupted, the control register content to be set to the default value, and all channels to be switched into sample mode.

When the device is powered up, the POR sets the device in default mode when AVDD reaches 1.5 V. When the device is powered down, the POR circuit requires AVDD to remain below 125 mV at least 350 ms to ensure proper discharging of internal capacitors and to ensure correct behavior of the device when powered up again. If the AVDD drops below 400 mV but remains above 125 mV (see the undefined zone in Figure 40), the internal POR capacitor does not discharge fully and the device requires a pin-controlled reset to perform correctly after the recovery of AVDD.

ADS8556 ADS8557 ADS8558 ai_por_levels_bas404.gif Figure 40. POR: Relevant Voltage Levels

The entire device, except the digital interface, can be powered down by pulling the STBY pin low (pin 24). Because the digital interface section remains active, data can be retrieved when in stand-by mode. To power the part on again, the STBY pin must be brought high. The device is ready to start a new conversion after the 10 ms required to activate and settle the internal circuitry. This user-controlled approach can be used in applications that require lower data throughput rates and lowest power dissipation. The content of CR is not changed during standby mode. A pin-controlled reset is not required after returning to normal operation.

Although the standby mode affects the entire device, each device channel pair can also be individually switched off by setting control register bits C[15:13] (PD_x). When reactivated, the relevant channel pair requires 10 ms to fully settle before starting a new conversion. The internal reference remains active, except all channels are powered down at the same time.

In partial power-down mode, each of the three channel pairs of the ADS855x can be individually put into a power-saving condition that reduces the current requirement to 2 mA per channel pair by bringing the corresponding CONVST_x signal low during an ongoing conversion when BUSY is high. The relevant channel pair is activated again by issuing a RESET pulse (to avoid loss of data from the active channels, this RESET pulse must be generated after retrieving the latest conversion results). The next rising edge of the CONVST_x signal must be issued at least six conversion cycle periods after the reset pulse and starts a new conversion; see Figure 41. The internal reference remains active during the partial power-down mode.

The auto-NAP power-down mode is enabled by asserting the A-NAP bit (C22) in the control register. If the auto-NAP mode is enabled, the ADS855x automatically reduces the current requirement to 6 mA after finishing a conversion; thus, the end of conversion actually activates the power-down mode. Triggering a new conversion by applying a positive CONVST_x edge puts the device back into normal operation, starts the acquisition of the analog input, and automatically starts a new conversion six conversion clock cycles later. Therefore, a complete conversion cycle takes 24.5 conversion clock cycles; thus, the maximum throughput rate in auto-NAP power-down mode is reduced to a maximum of 380 kSPS for the ADS8556, 395 kSPS for the ADS8557, and 420 kSPS for the ADS8558 in serial mode. In parallel mode, the maximum data rates are 500 kSPS for the ADS8556, 530 kSPS for the ADS8557, and 580 kSPS for the ADS8558. The internal reference remains active during the auto-NAP mode. Table 4 compares the analog current requirements of the devices in the different modes.

ADS8556 ADS8557 ADS8558 ai_tim_hw_pwrdwn_bas404.gif Figure 41. Partial Power-Down

Table 4. Maximum Analog Current (IAVDD) Demand of the ADS855x

OPERATIONAL MODE ANALOG CURRENT (IAVDD) ENABLED BY ACTIVATED BY NORMAL OPERATION TO POWER-DOWN DELAY RESUMED BY POWER-UP TO NORMAL OPERATION DELAY POWER-UP TO NEXT CONVERSION START TIME DISABLED BY
Normal operation 12 mA/channel pair (maximum data rate) Power on CONVST_x — — — — Power off
Partial power-down of channel pair x 2 mA (channel pair x) Power on CONVST_x low while BUSY is high At falling edge of BUSY RESET pulse Immediate 6 × tCCLK Power off
Auto-NAP 6 mA A-NAP = 1 (CR bit) Each end of conversion At falling edge of BUSY CONVST_x Immediate 6 × tCCLK A-NAP = 0 (CR bit)
Power-down of channel pair x 16 μA (channel pair x) HW/SW = 1 PD_x = 1 (CR bit) Immediate PD_x = 0 (CR bit) Immediate after completing register update 10 ms HW/SW = 0
Stand-by 50 μA Power on STBY = 0 Immediate STBY = 1 Immediate 10 ms Power off

7.5 Register Maps

7.5.1 Control Register (CR); Default Value = 0x000003FF

The control register settings can only be changed in software mode and are not affected when switching to hardware mode thereafter. The register values are independent from input pin settings. Changes are active with the rising edge of WR in parallel interface mode or with the 32nd falling SCLK edge of the access in which the register content is updated in serial mode. Optionally, the register can also be partially updated by writing only the upper eight bits (C[31:24]). The control register update options are provided in Figure 42. The CR content is defined in Table 5.

ADS8556 ADS8557 ADS8558 ai_tim_ctrl_update_bas404.gif Figure 42. Control Register Update Options

Table 5. Control Register (CR)

BIT NAME DESCRIPTION ACTIVE IN HARDWARE MODE
C31 CH_C 0 = Channel pair C disabled for next conversion (default)
1 = Channel pair C enabled		 No
C30 CH_B 0 = Channel pair B disabled for next conversion (default)
1 = Channel pair B enabled		 No
C29 CH_A 0 = Channel pair A disabled for next conversion (default)
1 = Channel pair A enabled		 No
C28 RANGE_C 0 = Input voltage range selection for channel pair C: 4 VREF (default)
1 = Input voltage range selection for channel pair C: 2 VREF 		No
C27 RANGE_B 0 = Input voltage range selection for channel pair B: 4 VREF (default)
1 = Input voltage range selection for channel pair B: 2 VREF 		No
C26 RANGE_A 0 = Input voltage range selection for channel pair A: 4 VREF (default)
1 = Input voltage range selection for channel pair A: 2 VREF 		No
C25 REFEN 0 = Internal reference source disabled (default)
1 = Internal reference source enabled		 No
C24 REFBUF 0 = Internal reference buffers enabled (default)
1 = Internal reference buffers disabled		 No
C23 SEQ 0 = Sequential convert start mode disabled (default)
1 = Sequential convert start mode enabled (bit 11 must be '1' in this case)		 No
C22 A-NAP 0 = Normal operation (default)
1 = Auto-NAP feature enabled		 Yes
C21 BUSY/INT 0 = BUSY/INT pin in normal mode (BUSY) (default)
1 = BUSY/INT pin in interrupt mode (INT)		 Yes
C20 BUSY L/H 0 = BUSY active high when INT is active low (default)
1 = BUSY active low when INT is active high		 Yes
C19 Don’t use This bit is always set to '0' —
C18 VREF 0 = Internal reference voltage: 2.5 V (default)
1 = Internal reference voltage: 3 V		 Yes
C17 READ_EN 0 = Normal operation (conversion results available on SDO_x) (default)
1 = Control register contents output on SDO_x with next access		 Yes
C16 C23:0_EN 0 = Control register bits C[31:24] update only (serial mode only) (default)
1 = Entire control register update enabled (serial mode only)		 Yes
C15 PD_C 0 = Normal operation (default)
1 = Power-down for channel pair C enabled (bit 31 must be '0' in this case)		 Yes
C14 PD_B 0 = Normal operation (default)
1 = Power-down for channel pair B enabled (bit 30 must be '0' in this case)		 Yes
C13 PD_A 0 = Normal operation (default)
1 = Power-down for channel pair A enabled (bit 29 must be '0' in this case)		 Yes
C12 Don't use This bit is always '0' —
C11 CLKSEL 0 = Normal operation with internal conversion clock (mandatory in hardware mode) (default)
1 = External conversion clock (applied through pin 27) used		 No
C10 CLKOUT_EN 0 = Normal operation (default)
1 = Internal conversion clock available at pin 27		 No
C9 REFDAC[9] Bit 9 (MSB) of reference DAC value; default = 1 Yes
C8 REFDAC[8] Bit 8 of reference DAC value; default = 1 Yes
C7 REFDAC[7] Bit 7 of reference DAC value; default = 1 Yes
C6 REFDAC[6] Bit 6 of reference DAC value; default = 1 Yes
C5 REFDAC[5] Bit 5 of reference DAC value; default = 1 Yes
C4 REFDAC[4] Bit 4 of reference DAC value; default = 1 Yes
C3 REFDAC[3] Bit 3 of reference DAC value; default = 1 Yes
C2 REFDAC[2] Bit 2 of reference DAC value; default = 1 Yes
C1 REFDAC[1] Bit 1 of reference DAC value; default = 1 Yes
C0 REFDAC[0] Bit 0 (LSB) of reference DAC value; default = 1 Yes