Product details


Resolution (Bits) 16 Number of input channels 6 Sample rate (Max) (kSPS) 630 Interface type Parallel, Byte-Wide, SPI Architecture SAR Input type Single-Ended Multi-channel configuration Simultaneous Sampling Rating Catalog Reference mode Ext, Int Input range (Max) (V) 12 Input range (Min) (V) -12 Features Daisy-Chainable, Oscillator Operating temperature range (C) -40 to 125 Power consumption (Typ) (mW) 335 Analog voltage AVDD (Min) (V) 4.5 SNR (dB) 91.5 Analog voltage AVDD (Max) (V) 5.5 INL (Max) (+/-LSB) 3 Digital supply (Min) (V) 2.7 Digital supply (Max) (V) 5.5 open-in-new Find other Precision ADCs (<=10MSPS)

Package | Pins | Size

LQFP (PM) 64 100 mm² 10 x 10 open-in-new Find other Precision ADCs (<=10MSPS)


  • Family of 16-, 14-, 12-Bit, Pin- and
    Software-Compatible ADCs
  • Six SAR ADCs Grouped in Three Pairs
  • Maximum Data Rate Per Channel with Internal
    Conversion Clock and Reference:
    ADS8556: 630 kSPS (PAR) or 450 kSPS (SER)
    ADS8557: 670 kSPS (PAR) or 470 kSPS (SER)
    ADS8558: 730 kSPS (PAR) or 500 kSPS (SER)
  • Maximum Data Rate with External Conversion
    Clock and Reference:
    800 kSPS (PAR) or 530 kSPS (SER)
  • Pin-Selectable or Programmable Input Voltage
    Ranges: Up to ±12 V
  • Excellent Signal-to-Noise Performance:
    ADS8556: 91.5 dB, ADS8667: 85 dB,
    ADS8668: 73.9 dB
  • Programmable and Buffered Internal Reference:
    0.5 V to 2.5 V and 0.5 V to 3.0 V
  • Comprehensive Power-Down Modes:
    • Deep Power-Down (Standby Mode)
    • Partial Power-Down
    • Auto-Nap Power-Down
  • Selectable Parallel or Serial Interface
  • Operating Temperature Range: –40°C to 125°C
open-in-new Find other Precision ADCs (<=10MSPS)


The ADS855x contains six low-power, 16-, 14-, or 12-bit, successive approximation register (SAR) based analog-to-digital converters (ADCs) with true bipolar inputs. Each channel contains a sample-and-hold circuit that allows simultaneous high-speed multi-channel signal acquisition.

The ADS855x supports data rates of up to 730 kSPS in parallel interface mode or up to 500 kSPS if the serial interface is used. The bus width of the parallel interface can be set to eight or 16 bits. In serial mode, up to three output channels can be activated.

The ADS855x is specified over the full industrial temperature range of –40°C to 125°C and is available in an LQFP-64 package.

open-in-new Find other Precision ADCs (<=10MSPS)

Technical documentation

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Type Title Date
* Data sheet ADS855x 16-, 14-, 12-Bit, Six-Channel, Simultaneous Sampling Analog-to-Digital Converters datasheet (Rev. D) Feb. 03, 2016
Application note A Numerical Protection Relay Solution (Rev. A) Jul. 26, 2018
White paper Voltage-reference impact on total harmonic distortion Aug. 01, 2016
E-book Best of Baker's Best: Precision Data Converters -- SAR ADCs May 21, 2015
Application note Driver Circuit Design Considerations for ADS855x Aug. 27, 2012
Application note Determining Minimum Acquisition Times for SAR ADCs, part 2 Mar. 17, 2011

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The ADS8555 evaluation module (EVM) performance demonstration kit (PDK) is a platform for evaluating the ADS855x family of six-channel simultaneous-sampling analog-to-digital converters (ADCs). ADS855x products include an integrated voltage reference and can accommodate ±12-V inputs.

ADS8555EVM-PDK (...)

  • Includes hardware and software required for diagnostic testing, as well as accurate performance evaluation of the ADS855x family
  • External ±15-V power supply required (not included); use common lab power supply
  • ±10-V and ±5-V input range with 2.5-V voltage reference; ±12-V and (...)

Design tools & simulation

SBAM011B.ZIP (80 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide
Analog-to-digital converter (ADC) input driver design tool supporting multiple input types
ADC-INPUT-CALC ADC-INPUT-CALC is an online tool that provides support for designing the input buffer to an analog-to-digital converter (ADC). It offers 24 different op-amp based buffer circuits that can be used to drive an ADC input. The available topologies cover differential, single-ended and transformer-coupled (...)
Analog engineer's calculator
ANALOG-ENGINEER-CALC — The Analog Engineer’s Calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting op-amp gain with feedback (...)
  • Expedites circuit design with analog-to-digital converters (ADCs) and digital-to-analog converters (DACs)
    • Noise calculations
    • Common unit translation
  • Solves common amplifier circuit design problems
    • Gain selections using standard resistors
    • Filter configurations
    • Total noise for common amplifier configurations
  • (...)
Jitter and SNR Calculator for ADCs
JITTER-SNR-CALC JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.

CAD/CAE symbols

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LQFP (PM) 64 View options

Ordering & quality

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  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
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  • Qualification summary
  • Ongoing reliability monitoring

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