SBAS627 July   2015 ADS8674 , ADS8678


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs
      2. 8.3.2  Analog Input Impedance
      3. 8.3.3  Input Overvoltage Protection Circuit
      4. 8.3.4  Programmable Gain Amplifier (PGA)
      5. 8.3.5  Second-Order, Low-Pass Filter (LPF)
      6. 8.3.6  ADC Driver
      7. 8.3.7  Multiplexer (MUX)
      8. 8.3.8  Reference
        1. Internal Reference
        2. External Reference
      9. 8.3.9  Auxiliary Channel
        1. Input Driver for the AUX Channel
      10. 8.3.10 ADC Transfer Function
      11. 8.3.11 Alarm Feature
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Interface
        1. Digital Pin Description
          1. CS (Input)
          2. SCLK (Input)
          3. SDI (Input)
          4. SDO (Output)
          5. DAISY (Input)
          6. RST/PD (Input)
        2. Data Acquisition Example
        3. Host-to-Device Connection Topologies
          1. Daisy-Chain Topology
          2. Star Topology
      2. 8.4.2 Device Modes
        1. Continued Operation in the Selected Mode (NO_OP)
        2. Frame Abort Condition (FRAME_ABORT)
        3. STANDBY Mode (STDBY)
        4. Power-Down Mode (PWR_DN)
        5. Auto Channel Enable with Reset (AUTO_RST)
        6. Manual Channel n Select (MAN_Ch_n)
        7. Channel Sequencing Modes
        8. Reset Program Registers (RST)
    5. 8.5 Register Maps
      1. 8.5.1 Command Register Description
      2. 8.5.2 Program Register Description
        1. Program Register Read/Write Operation
        2. Program Register Map
        3. Program Register Descriptions
          1. Auto-Scan Sequencing Control Registers
            1. Auto-Scan Sequence Enable Register (address = 01h)
            2. Channel Power Down Register (address = 02h)
          2. Device Features Selection Control Register (address = 03h)
          3. Range Select Registers (addresses 05h-0Ch)
          4. Alarm Flag Registers (Read-Only)
            1. ALARM Overview Tripped-Flag Register (address = 10h)
            2. Alarm Flag Registers: Tripped and Active (address = 11h to 14h)
          5. Alarm Threshold Setting Registers
          6. Command Read-Back Register (address = 3Fh)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Phase-Compensated, 8-Channel, Multiplexed Data Acquisition System for Power Automation
        1. Design Requirements
        2. Detailed Design Procedure
      2. 9.2.2 14-Bit, 8-Channel, Integrated Analog Input Module for Programmable Logic Controllers (PLCs)
        1. Design Requirements
        2. Detailed Design Procedure
  10. 10Power-Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Figure 128 illustrates a PCB layout example for the ADS8674 and ADS8678.

  • Partition the PCB into analog and digital sections. Care must be taken to ensure that the analog signals are kept away from the digital lines. This layout helps keep the analog input and reference input signals away from the digital noise. In this layout example, the analog input and reference signals are routed on the lower side of the board and the digital connections are routed on the top side of the board.
  • Using a single dedicated ground plane is strongly encouraged.
  • Power sources to the ADS8674 and ADS8678 must be clean and well-bypassed. TI recommends using a
    1-μF, X7R-grade, 0603-size ceramic capacitor with at least a 10-V rating in close proximity to the analog (AVDD) supply pins. For decoupling the digital (DVDD) supply pin, a 10-μF, X7R-grade, 0805-size ceramic capacitor with at least a 10-V rating is recommended. Placing vias between the AVDD, DVDD pins and the bypass capacitors must be avoided. All ground pins must be connected to the ground plane using short, low impedance paths.
  • There are two decoupling capacitors used for the REFCAP pin. The first is a small, 1-μF, X7R-grade, 0603-size ceramic capacitor placed close to the device pins for decoupling the high-frequency signals and the second is a 22-µF, X7R-grade, 1210-size ceramic capacitor to provide the charge required by the reference circuit of the device. Both of these capacitors must be directly connected to the device pins without any vias between the pins and capacitors.
  • The REFIO pin also must be decoupled with a 10-µF ceramic capacitor, if the internal reference of the device is used. The capacitor must be placed close to the device pins.
  • For the auxiliary channel, the fly-wheel RC filter components must be placed close to the device. Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.

11.2 Layout Example

ADS8674 ADS8678 apps_layout_sbas582.gifFigure 128. Board Layout for the ADS8674 and ADS8678